公开(公告)号：WO2012019768A1

公开(公告)日：2012-02-16

申请号：PCT/EP2011/004030

申请日：2011-08-11

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: G06K19/073

CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

Abstract: The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

Abstract translation: 本发明涉及一种包括至少一个集成电路（24a）和收发器/应答器电路（30）的安全系统，所述至少一个集成电路（24a）设置有天线（36），用于与收发器/应答器 电路（30），与所述至少一个集成电路（24a）相关联的禁止元件（24b，44,44a，44b），用于禁止与所述收发器/应答器电路（30）的通信并且用于保护包含在所述收发器/ 至少一个集成电路（24a）。 有利地，禁止元件（24b,44,44a，44b）是电磁抑制元件，所述安全系统还包括与所述至少一个集成电路（24a）的天线（36）相关联的耦合元件（22） 用于临时停用所述电磁抑制元件（24b,44,44a，44b）以允许所述至少一个集成电路（24a）与所述收发器/应答器电路（30）之间的通信。

公开(公告)号：WO2010015388A1

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005655

申请日：2009-08-05

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

Abstract translation: 本发明涉及用于在电子或电磁测试（例如EMWS或EWS或WLBI测试）中并行供电的电路架构，每个电子设备（2）均集成在相同的半导体晶片（1）上，其中 电子器件（1）通过积分技术整齐地设置在半导体晶片（1）上并且具有由分隔划线（7）限定的边缘（5）。 有利地，根据本发明，电路架构包括： - 至少一个导电栅格（4），其将至少一组电子设备（2）互连并且具有到该组的设备的外部（14）的部分，以及 部分是内部（13）到组的装置; 导电栅格（4）的外部部分（14）也沿着分隔划线（7）延伸; 所述内部部分（13）在所述组的装置的至少一部分内延伸; 在外部部分（14）和导电栅格（4）的内部部分（13）之间的互连焊盘（6）设置在该组的至少一部分器件上，互连焊盘（6）连同 内部和外部部分，该组的不同电子设备（2）共同的电源线。

公开(公告)号：WO2010076187A3

公开(公告)日：2010-07-08

申请号：PCT/EP2009/067156

申请日：2009-12-15

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: H01L23/66 ,  H01L23/48 ,  H01L21/66 ,  H01L23/544 ,  H01L25/065

Abstract: An integrated electronic device (1) having a body (9) of semiconductor material and a first antenna (3;3a) which enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna (3b,3c). The integrated electronic device (1) has a first via (4;4a- 4d;50;50a;53) of magnetic material arranged at least in part inside the body (9), which forms, in use, a communication channel between the first antenna (3;3a) and the further antenna (3b,3c).

公开(公告)号：WO2010046724A1

公开(公告)日：2010-04-29

申请号：PCT/IB2008/003660

申请日：2008-10-22

Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  STMICROELECTRONICS S.R.L. ,  TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

IPC: G05B19/418 ,  G01R31/28

CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

Abstract: The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

Abstract translation: 本发明涉及一种用于改进测量链的重复性和再现性检查的方法，特别是通过半导体器件测试进行质量控制的方法，其中为多个和不同的器件提供测试步骤以通过 测量系统包括测试装置（ATE）和待测量的每个装置之间的测量单元的至少一个级联。 有利地，该方法包括以下步骤：检查构成级联测量链的一部分的每种类型的单元的重复性和重复性; 然后在各测量链之间进行整体的相关性，以检查重复性和再现性，使用相应的测量装置。

公开(公告)号：WO2012090188A1

公开(公告)日：2012-07-05

申请号：PCT/IB2011/056033

申请日：2011-12-30

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: A61F9/08

CPC classification number: A61F2/14 ,  A61F2/148 ,  A61F9/08 ,  A61F2250/0002 ,  A61N1/0543 ,  A61N1/36 ,  A61N1/36046

Abstract: A retinal prosthesis including an electronic stimulation unit (40) housed inside an eye and including: a plurality of electrodes (62); an electronic control circuit (92, 102), which is electrically connected to the electrodes and supplies to the electrodes electrical stimulation signals designed to stimulate a portion of a retina of the eye; and a local antenna (114) connected to the electronic control circuit. The retinal prosthesis further includes an electromagnetic expansion (35) housed inside the eye and formed by a first expansion antenna (44) and a second expansion antenna (46) electrically connected together, the first expansion antenna being magnetically or electromagnetically coupled to an external antenna (38), the second expansion antenna being magnetically or electromagnetically coupled to the local antenna, the electromagnetic expansion moreover receiving an electromagnetic supply signal transmitted by the external antenna and generating a corresponding replica signal.

Abstract translation: 一种视网膜假体，包括容纳在眼睛内的电子刺激单元（40），包括：多个电极（62）; 电子控制电路（92,102），其电连接到电极并向电极提供设计成刺激眼睛的视网膜的一部分的电刺激信号; 以及连接到电子控制电路的本地天线（114）。 视网膜假体还包括容纳在眼睛内并由电连接在一起的第一扩展天线（44）和第二扩展天线（46）形成的电磁膨胀（35），第一扩展天线被磁性或电磁耦合到外部天线 （38），所述第二扩展天线与所述本地天线进行磁或电磁耦合，所述电磁膨胀还接收由所述外部天线发送的电磁供给信号并产生对应的复制信号。

公开(公告)号：WO2012084295A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/068359

申请日：2011-10-20

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  MURARI, Bruno

Inventor： PAGANI, Alberto ,  MURARI, Bruno

IPC: G01N27/20 ,  G01N33/38 ,  G01L1/18

CPC classification number: G01N27/00 ,  G01L1/26 ,  G01M5/0083

Abstract: Device (100) for detecting and monitoring local parameters within a solid structure (300). The device comprises an integrated detection module (1) made on a single chip, having an integrated functional circuitry portion (16) comprising at least one integrated sensor (10) and an integrated antenna (11), and electromagnetic means (2) for transmitting/receiving signals and energy exchange. The integrated functional circuitry portion (16) comprises a functional surface (18) facing towards the outside of the chip. A passivation layer (15) is arranged to completely cover at least the functional surface (18), so that the integrated detection module (1) is entirely hermetically sealed and galvanically insulated from the surrounding environment. The integrated antenna (11), the electromagnetic means (2) and the remote antenna (221) are operatively connected wirelessly through magnetic or electromagnetic coupling.

Abstract translation: 用于检测和监测固体结构（300）内的局部参数的装置（100）。 该装置包括在单个芯片上制成的集成检测模块（1），其具有包括至少一个集成传感器（10）和集成天线（11）的集成功能电路部分（16），以及电磁装置（2） /接收信号和能量交换。 集成功能电路部分（16）包括面向芯片外部的功能表面（18）。 钝化层（15）布置成完全覆盖至少功能表面（18），使得集成检测模块（1）完全被气密密封并与周围环境电隔离。 集成天线（11），电磁装置（2）和远程天线（221）通过磁或电磁耦合无线地可操作地连接。

公开(公告)号：WO2012084207A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/006449

申请日：2011-12-20

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/522

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention in a single structure combines a pad comprising a connection terminal suitable for connecting the circuit elements integrated in a chip to circuits outside of the chip itself and at least one condenser. By combining a connection pad and a condenser in a single structure it is possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the condenser itself. In this way, the costs and size of the chip can be reduced.

Abstract translation: 本发明的单一结构组合了包括适于将集成在芯片中的电路元件连接到芯片本身外部的电路的连接端子和至少一个冷凝器的焊盘。 通过在单一结构中组合连接焊盘和冷凝器，可以减少芯片的总面积，否则由于冷凝器本身的存在，否则常见的集成电路将会更大。 以这种方式，可以降低芯片的成本和尺寸。

公开(公告)号：WO2011101393A1

公开(公告)日：2011-08-25

申请号：PCT/EP2011/052319

申请日：2011-02-16

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/544

CPC classification number: G01R31/275 ,  G01R31/2853 ,  H01L21/76898 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A testing system for carrying out electrical testing of at least a through via (10) extending, at least in part, through a substrate (3) of a body (2) of semiconductor material and having a first end (10b) buried within the substrate (3) and not accessible from the outside of the body (2). The testing system has an electrical test circuit (22) integrated in the body (2) and electrically coupled to the through via (10) and to electrical-connection elements (8) carried by the body (2) for electrical connection towards the outside; the electrical test circuit (22) has a buried microelectronic structure (28) integrated in the substrate (3) so as to be electrically coupled to the first end (10b) of the through via (10), thereby closing an electrical path within the substrate (3) and enabling detection of at least one electrical parameter of the through via (10) through the electrical-connection means (8).

Abstract translation: 至少一个至少部分通过半导体材料的主体（2）的基板（3）延伸的通孔（10）进行电气测试的测试系统，并且具有埋在该半导体材料的第一端（10b）内的第一端 基板（3）并且不能从主体（2）的外部接近。 测试系统具有集成在主体（2）中并电耦合到通孔（10）的电测试电路（22）和由主体（2）承载的电连接元件（8），用于电连接到外部 ; 电测试电路（22）具有集成在基板（3）中的埋入微电子结构（28），以便电连接到通孔（10）的第一端（10b），从而封闭通孔 基板（3），并且能够通过电连接装置（8）检测通孔（10）的至少一个电参数。

公开(公告)号：WO2009080760A1

公开(公告)日：2009-07-02

申请号：PCT/EP2008/068047

申请日：2008-12-19

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: G01R1/073

CPC classification number: G01R31/2889 ,  B62M25/04 ,  G01R1/0491 ,  G01R1/06727 ,  G01R1/07342

Abstract: A probe card (105') adapted for testing at least one integrated circuit integrated on corresponding at least one die (145) of a semiconductor material wafer, the probe card including a board (125') adapted for the coupling to a tester apparatus, and a plurality of probes (225) coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units (135'), each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test (145), the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract translation: 一种探针卡（105'），适用于测试集成在半导体材料晶片的相应的至少一个管芯（145）上的至少一个集成电路，所述探针卡包括适于耦合到测试仪器的板（125'）， 以及耦合到所述板的多个探针（225），其中所述探针卡包括多个可更换的基本单元（135'），每个所述探针卡包括至少一个所述探针，用于接触集成电路的外部可接近的端子 所述多个可更换基本单元被布置成对应于包含要测试的集成电路的半导体材料晶片上的至少一个管芯的布置。

公开(公告)号：WO2014006570A8

公开(公告)日：2014-01-09

申请号：PCT/IB2013/055430

申请日：2013-07-02

Applicant: STMICROELECTRONICS S.R.L.

Inventor： PAGANI, Alberto ,  MOTTA, Alessandro ,  LOI, Sara

IPC: G02B6/12 ,  G02B6/43

Abstract: An integrated electronic device, delimited by a first surface (S 1 ) and by a second surface (S 2 ) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.