公开(公告)号：US08704358B2

公开(公告)日：2014-04-22

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L23/04

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10μm，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连电平的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US20140061723A1

公开(公告)日：2014-03-06

申请号：US14017024

申请日：2013-09-03

Applicant: STMicroelectronics S.A.

Inventor： Vincent Quenette

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract translation: 一种MOS晶体管，包括U形沟道形成半导体区域和具有相同U形的源极和漏极区域，其位于其任一侧上的沟道形成区域，沟道形成半导体区域的内表面涂覆有导电 栅极，插入栅极绝缘体。

公开(公告)号：US20130201766A1

公开(公告)日：2013-08-08

申请号：US13754427

申请日：2013-01-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Anis Feki

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/10 ,  G11C7/00 ,  G11C7/18 ,  G11C8/12 ,  G11C8/14 ,  G11C8/16

Abstract: A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

Abstract translation: 易失性存储器包括执行数据写入和读取操作的易失性存储器单元。 存储单元以行和列排列并且分布在每列的第一分离的存储单元组中。 对于每列，存储器包括专用于写操作并连接到列的所有存储器单元的写位线，以及专用于读操作的读位线。 每个读位线连接到第一组存储器单元之一的所有存储单元。 列中的每个存储单元连接到单个读取位线。

公开(公告)号：US20040252554A1

公开(公告)日：2004-12-16

申请号：US10726263

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C016/04

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

公开(公告)号：US20040251781A1

公开(公告)日：2004-12-16

申请号：US10814619

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Guillaume Bouche ,  Pascal Ancey ,  Gregory Caruyer

IPC: H01L041/04

CPC classification number: B81B3/0078 ,  B81B2201/0271 ,  B81B2201/032 ,  B81B2203/0109 ,  H01G5/16 ,  H03H9/172 ,  H03H2009/02181

Abstract: A device comprising a resonator formed of a piezoelectric layer sandwiched between two metal electrodes, the resonator being laid on a suspended beam, the device comprising means for deforming said beam by the difference in thermal expansion coefficients.

Abstract translation: 一种包括由夹在两个金属电极之间的压电层形成的谐振器的装置，所述谐振器被放置在悬挂梁上，所述装置包括用于使所述光束变形所述热膨胀系数的差异的装置。

公开(公告)号：US20040246800A1

公开(公告)日：2004-12-09

申请号：US10860080

申请日：2004-06-03

Applicant: STMicroelectronics S.A.

Inventor： Franck Genevaux ,  Francois Jacquet

IPC: G11C007/00

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C2207/065

Abstract: A sense amplifier connected to first and second bit lines, comprising means for precharging said bit lines to a high voltage, means for connecting one or the other of the bit lines to a memory cell, said connection causing according to the state of the memory cell a maintaining of the bit line at the high voltage or a voltage reduction, first and second transistors respectively controlled by the first and second bit lines, and, in series with the first and second transistors, a controllable means for the current through the transistor controlled by the bit line connected to the memory cell to be greater than the current through the other transistor when the voltages of the two bit lines are at the high voltage.

Abstract translation: 连接到第一和第二位线的感测放大器包括用于将所述位线预充电到高电压的装置，用于将一个或另一个位线连接到存储器单元的装置，所述连接根据存储器单元的状态 分别由第一和第二位线控制的高电压或电压降低的位线的保持，以及与第一和第二晶体管串联的用于通过晶体管控制的电流的可控制装置 当两个位线的电压处于高电压时，连接到存储单元的位线大于通过另一个晶体管的电流。

公开(公告)号：US20040212410A1

公开(公告)日：2004-10-28

申请号：US10776931

申请日：2004-02-11

Applicant: STMicroelectronics S.A.

Inventor： Mostafa Ghazali ,  Pierre-Olivier Jouffre

IPC: H03L007/06

CPC classification number: H03L7/18 ,  H03L7/0891 ,  H03L7/0996

Abstract: A phase-locked loop comprising a comparator generating a control voltage depending on the phase-shift between a reference signal and a feedback signal, an oscillator controlled by the control voltage, generating several phase-shifted signals of same period, one of which forms the output signal of the phase-locked loop, a multiplexer capable of providing any of the phase-shifted signals to the input of a divider, the output of which forms the feedback signal, and a means controlling the multiplexer to successively provide fractions of the phase-shifted signals, so that the divider receives a signal having an average period equal to a real fraction of the period of the phase-shifted signals.

Abstract translation: 一种锁相环，包括比较器，其产生取决于参考信号和反馈信号之间的相移的控制电压，由控制电压控制的振荡器，产生相同周期的多个相移信号，其中之一形成 输出信号的多路复用器，能够将任何相移信号提供给分频器的输入，分频器的输出形成反馈信号，以及控制多路复用器的装置，以连续地提供相位的分数 转换信号，使得分频器接收具有等于相移信号的周期的实际分数的平均周期的信号。

公开(公告)号：US20040193836A1

公开(公告)日：2004-09-30

申请号：US10701384

申请日：2003-11-04

Applicant: STMICROELECTRONICS S.A.

Inventor： Bernard Ramanadin

IPC: G06F015/00

CPC classification number: G06F13/385

Abstract: A resynchronization module for use in an electronic system comprising a system bus comprises pipeline means of for pipelining the transactions intended for and/or originating from the associated functional module. The pipeline means comprise a first buffer circuit and at least one second buffer circuit, which are connected in parallel, and are each, adapted for storing transaction data of a specific transaction.

Abstract translation: 用于包括系统总线的电子系统的再同步模块包括用于流水线化用于和/或源自相关联的功能模块的事务的流水线装置。 流水线装置包括并联连接的第一缓冲电路和至少一个第二缓冲电路，并且各自适于存储特定事务的交易数据。

公开(公告)号：US20040164788A1

公开(公告)日：2004-08-26

申请号：US10721058

申请日：2003-11-24

Applicant: STMicroelectronics S.A.

Inventor： Jean Devin

IPC: G05F001/10

CPC classification number: H02H9/046

Abstract: An integrated circuit having a voltage generator supplying a determined voltage, a voltage-limiting circuit arranged at the output of the voltage generator, the voltage-limiting circuit having at least one PN junction formed by a diode-arranged MOS transistor, the PN junction having a breakdown voltage defining a threshold for triggering the voltage-limiting circuit as from which the PN junction is on by avalanche effect, at least one load in series with the PN junction for limiting an avalanche current passing through the PN junction when the PN junction is on, and at least one switch in parallel with the PN junction and the load, the switch arranged in the open state when the PN junction is off and to be in the closed state when the PN junction is on.

Abstract translation: 一种具有提供确定电压的电压发生器的集成电路，布置在电压发生器的输出端的限压电路，该限压电路具有由二极管配置的MOS晶体管形成的至少一个PN结，该PN结具有 限定阈值的击穿电压，用于触发由PN结接通的雪崩效应的电压限制电路，与PN结串联的至少一个负载，用于限制当PN结处于PN结处时通过PN结的雪崩电流 以及与PN结和负载并联的至少一个开关，当PN结关闭时，开关布置成处于断开状态，并且当PN结接通时处于闭合状态。

公开(公告)号：US20040160715A1

公开(公告)日：2004-08-19

申请号：US10726259

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Christophe Premont ,  Louis Tallaron ,  Severin Trochut

IPC: H02H003/20

CPC classification number: H02M3/157 ,  H02M3/1584 ,  Y10T307/696 ,  Y10T307/702

Abstract: The switch mode power supply includes a switching cell SC controllable cyclically and including only one inductive element L and several individually selectable outputs. During each conduction cycle, a total power level corresponding to the sum of the individual power levels respectively required by all the outputs OUTi during this cycle is injected into the inductive element L, the outputs requiring a non-zero individual power level are selected successively and in a predetermined order that is identical for all the cycles, and, at each selected output, the corresponding individual power level is produced.

Abstract translation: 开关模式电源包括周期性可控的切换单元SC，并且仅包括一个电感元件L和几个可单独选择的输出。 在每个导通周期期间，对应于在该周期期间所有输出OUTi分别要求的各个功率电平之和的总功率电平被注入到电感元件L中，连续选择需要非零个别功率电平的输出， 以对于所有周期相同的预定顺序，并且在每个选择的输出处产生相应的单独功率电平。