INTEGRATED SENSOR AND METHOD OF TIMING MONITORING IN AN INTEGRATED SENSOR

    公开(公告)号:US20240019475A1

    公开(公告)日:2024-01-18

    申请号:US18348993

    申请日:2023-07-07

    CPC classification number: G01R29/12 G01R23/02

    Abstract: The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.

    METHOD OF MANUFACTURING A STATOR FOR AN ELECTRIC MOTOR, STATOR, AND ELECTRIC MOTOR

    公开(公告)号:US20240014718A1

    公开(公告)日:2024-01-11

    申请号:US18345863

    申请日:2023-06-30

    CPC classification number: H02K15/026 H02K15/0068 H02K2215/00

    Abstract: A stator for an electric actuator or motor, including: a solid body; a ferromagnetic core region between the layers of semiconductor material, electrically insulated from the layers of semiconductor material; a plurality of conductive through vias through the solid body; a first plurality of conductive strips, which extend parallel to one another above the core; and a second plurality of conductive strips, which extend parallel to one another above the core and opposite to the first plurality of conductive strips; wherein the first plurality of conductive strips, the plurality of conductive through vias, and the second plurality of conductive strips form a winding or coil of the stator.

    SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD OF MANUFACTURE

    公开(公告)号:US20240006277A1

    公开(公告)日:2024-01-04

    申请号:US18369652

    申请日:2023-09-18

    CPC classification number: H01L23/49589 H01L21/4825 H01L23/49503 H01L23/4952

    Abstract: Disclosed herein is a method for manufacturing a semiconductor product package. The method includes arranging a leadframe with one or more leads such that each lead has an inner end facing a portion of a die-pad, attaching a semiconductor chip to the die-pad, attaching a first electrically conductive mass to the die-pad such that it is aligned with the inner end of a lead protruding over the die-pad, attaching an electrical component to the first electrically conductive mass such that a longitudinal axis of the electrical component is arranged traverse to the die-pad, and coupling a second electrically conductive mass between a termination of the electrical component and the inner end of the lead.

    ACCELERATION OF 1X1 CONVOLUTIONS IN CONVOLUTIONAL NEURAL NETWORKS

    公开(公告)号:US20230418559A1

    公开(公告)日:2023-12-28

    申请号:US17847817

    申请日:2022-06-23

    CPC classification number: G06F7/523 G06F7/50

    Abstract: A convolutional accelerator includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and mode control circuitry. In a first mode of operation, the mode control circuitry stores feature data in a feature line buffer and stores kernel data in a kernel buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. In a second mode of operation the mode control circuitry stores feature data in the kernel buffer and stores kernel data in the feature line buffer. The data stored in the buffers is transferred to the MAC cluster of the convolutional accelerator for processing. The second mode of operation may be employed to efficiently process 1×N kernels, where N is an integer greater than or equal to 1.

    CENTRALIZED DIGITAL MUTE AND VOLUME CONTROL
    309.
    发明公开

    公开(公告)号:US20230418548A1

    公开(公告)日:2023-12-28

    申请号:US17846586

    申请日:2022-06-22

    CPC classification number: G06F3/165

    Abstract: An audio device includes a gain step selection circuit that receives a different requested gain value and an associated requested step size from each of a plurality of sources, compares each requested gain value to a same feedback gain value and generates a polarity based thereupon, performs step polarization on each requested step size as a function of the generated polarity therefor to thereby generate a plurality of step values, and outputs a least of the plurality of step values as an output step value. An accumulator circuit generates a current input gain value based upon the output step value and the feedback gain value, and then updates the feedback gain value to be equal to the current input gain value. A normalizing circuit multiplies an input data value by the current input gain value and applies a truncation function to a result thereof to produce an output data value.

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