公开(公告)号：US20210160999A1

公开(公告)日：2021-05-27

申请号：US16697699

申请日：2019-11-27

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H05K1/02 ,  H05K1/16 ,  H05K3/12 ,  H05K3/40

Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.

公开(公告)号：US11011470B1

公开(公告)日：2021-05-18

申请号：US16667698

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

Abstract: Embodiments may relate to a microelectronic package that includes a substrate with an overmold material. The microelectronic package may include a die in the overmold material, and an inactive side of the die may be coupled with a face of the substrate. A through-mold via (TMV) may be present in the overmold material. The TMV may be communicatively coupled with the substrate, and an active side of the die may be communicatively coupled with the TMV by a trace in the overmold material. Other embodiments may be described or claimed.

公开(公告)号：US20210066265A1

公开(公告)日：2021-03-04

申请号：US16553544

申请日：2019-08-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan ,  Sivakumar Nagarajan ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  William James Lambert

IPC: H01L25/16 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H03F3/213 ,  H01G2/06 ,  H01G2/10

Abstract: Disclosed herein are tunable capacitor arrangements in integrated circuit (IC) package substrates, as well as related methods and devices. For example, in some embodiments, an IC package substrate may include a first embedded capacitor, a second embedded capacitor, and a fuse electrically coupled between the first embedded capacitor and the second embedded capacitor such that when the fuse is in a closed state, the first embedded capacitor and the second embedded capacitor are connected in parallel, and when the fuse is in an open state, the first embedded capacitor and the second embedded capacitor are not connected in parallel.

公开(公告)号：US20210066184A1

公开(公告)日：2021-03-04

申请号：US16554288

申请日：2019-08-28

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H01L49/02

Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

公开(公告)号：US10923429B2

公开(公告)日：2021-02-16

申请号：US16940024

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20210043544A1

公开(公告)日：2021-02-11

申请号：US16533152

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/427 ,  H01L23/38 ,  H01L23/373 ,  H01L23/31 ,  H01L23/66 ,  H01L23/48 ,  H03H9/46

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US10798817B2

公开(公告)日：2020-10-06

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/538 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K3/06 ,  H05K3/30 ,  H05K3/40 ,  H05K3/28

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.

公开(公告)号：US20200294939A1

公开(公告)日：2020-09-17

申请号：US16394905

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US10566672B2

公开(公告)日：2020-02-18

申请号：US15277504

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Sasha N. Oster ,  Johanna M. Swan ,  Georgios C. Dogiamis ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Telesphor Kamgaing

IPC: H01P5/10 ,  H01Q13/08

Abstract: The systems and methods described herein provide a traveling wave launcher system physically and communicably coupled to a semiconductor package and to a waveguide connector. The traveling wave launcher system includes a slot-line signal converter and a tapered slot launcher. The slot-line signal converter may be formed integral with the semiconductor package and includes a balun structure that converts the microstrip signal to a slot-line signal. The tapered slot launcher is communicably coupled to the slot-line signal converter and includes a planar first member and a planar second member that form a slot. The tapered slot launcher converts the slot-line signal to a traveling wave signal that is propagated to the waveguide connector.

公开(公告)号：US20200006236A1

公开(公告)日：2020-01-02

申请号：US16021966

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Andrew Paul Collins ,  Jianyong Xie ,  Sujit Sharan ,  Henning Braunisch ,  Aleksandar Aleksov

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.