公开(公告)号：US11961836B2

公开(公告)日：2024-04-16

申请号：US16147205

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Hyung-Jin Lee ,  Mark Armstrong ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Ayan Kar

IPC: H01L27/08 ,  H01L29/66 ,  H01L29/93 ,  H10B99/00

CPC classification number: H01L27/0808 ,  H01L29/66174 ,  H01L29/93 ,  H10B99/00

Abstract: An integrated circuit structure comprises one or more fins extending above a surface of a substrate over an N-type well. A gate is over and in contact with the one or more fins. A second shallow N-type doping is below the gate and above the N-type well.

公开(公告)号：US11538803B2

公开(公告)日：2022-12-27

申请号：US16221086

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Telesphor Kamgaing ,  Aleksandar Aleksov ,  Gerogios Dogiamis ,  Hyung-Jin Lee

IPC: H01L29/40 ,  H01L21/00 ,  H01L27/07 ,  H01L21/8238 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.

公开(公告)号：US11437706B2

公开(公告)日：2022-09-06

申请号：US16369452

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L25/065 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L23/552 ,  H01L25/00

Abstract: Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US11108433B2

公开(公告)日：2021-08-31

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

公开(公告)号：US20200273824A1

公开(公告)日：2020-08-27

申请号：US16369836

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Hyung-Jin Lee ,  Henning Braunisch ,  Richard Dischler

IPC: H01L23/66 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments may relate to a microelectronic package that includes a package substrate and a signal interconnect coupled with the face of the package substrate. The microelectronic package may further include a ground interconnect coupled with the face of the package substrate. The ground interconnect may at least partially surround the signal interconnect. Other embodiments may be described or claimed.

公开(公告)号：US20190097293A1

公开(公告)日：2019-03-28

申请号：US16186103

申请日：2018-11-09

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Henning Braunisch ,  Gilbert W. Dewey ,  Telesphor Kamgaing ,  Hyung-Jin Lee ,  Johanna M. Swan

IPC: H01P3/127 ,  H01P3/10 ,  H01P5/103

Abstract: There is disclosed in one example an electromagnetic wave launcher apparatus, including: an interface to an electromagnetic waveguide; a first launcher configured to launch a high-frequency electromagnetic signal onto a first cross-sectional portion of the waveguide; and a second launcher configured to launch a lower-frequency electromagnetic signal onto a second cross-sectional portion of the waveguide.

公开(公告)号：US10109551B2

公开(公告)日：2018-10-23

申请号：US14854487

申请日：2015-09-15

Applicant: Intel Corporation

Inventor： Cho-Ying Lu ,  Matthias Eberlein ,  Hyung-Jin Lee

IPC: H01L23/34 ,  H01L27/16

Abstract: Embodiments of the present disclosure provide techniques and configurations for integrally determining a parameter (e.g., temperature) of a die of an integrated circuit. In one instance, the apparatus may comprise a die including a first (e.g., remote) area and a second (e.g., local) area disposed at a distance from the first area, and circuitry to determine a parameter associated with the remote area of the die. The circuitry may include: a first sensing device disposed in the remote area, to provide first readings associated with the parameter; a second sensing device disposed in the local area, to provide second readings associated with the parameter; and a control module coupled with the sensing devices and disposed in the local area, to facilitate a determination of the parameter based on the first and second readings provided by the first and second sensing devices. Other embodiments may be described and/or claimed.

公开(公告)号：US11621334B2

公开(公告)日：2023-04-04

申请号：US16260600

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Said Rami ,  Hyung-Jin Lee ,  Surej Ravikumar ,  Kinyip Phoa

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L27/12 ,  G06F13/10

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

公开(公告)号：US11532574B2

公开(公告)日：2022-12-20

申请号：US16394905

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01L21/00 ,  H01L23/66 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/16 ,  H01P3/06 ,  H01P11/00

Abstract: Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US10855224B2

公开(公告)日：2020-12-01

申请号：US16369361

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Sachin Kalia ,  Satwik Patnaik ,  Hyung-Jin Lee ,  Ram Sadhwani

IPC: H03B5/12

Abstract: A voltage controlled oscillator (VCO) circuit is disclosed. The VCO circuit comprises a VCO tuning circuit comprising a primary inductive coil. In some embodiments, the VCO tuning circuit is configured to generate a VCO output signal at a first resonance frequency. The VCO circuit further comprises a filter circuit comprising a secondary inductive coil. In some embodiments, the filter circuit is configured to resonate at a second, different, resonance frequency, in order to filter a noise associated with the VCO tuning circuit. In some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are concentrically arranged with respect to one another. Further, in some embodiments, the primary inductive coil associated with the VCO tuning circuit and the secondary inductive coil associated with the filter circuit are magnetically decoupled with respect to one another.