公开(公告)号：US20240291387A1

公开(公告)日：2024-08-29

申请号：US18437919

申请日：2024-02-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Stefano PERROTTA ,  Salvatore Giuseppe PRIVITERA ,  Francesco PULVIRENTI

IPC: H02M3/335 ,  H02M1/00 ,  H02M3/00 ,  H02M3/338

CPC classification number: H02M3/33523 ,  H02M1/0054 ,  H02M3/01 ,  H02M3/3384

Abstract: Provided is a DC-DC converter with galvanic isolation comprising a resonant oscillator coupled to a primary winding of a galvanic isolation transformer. A rectifier is coupled to a secondary winding of the transformer to provide an output voltage. The DC-DC converter comprises a regulation loop configured to regulate an output voltage with respect to a reference voltage by controlling a current flowing in the resonant oscillator as a function of a result of a signal indicative of the comparison between the output voltage and the reference voltage. The resonant oscillator is configured to operate at a frequency, in particular tuned at sub-resonant point, in particular sub-harmonic frequency, below a resonance frequency of the resonant oscillator which maximizes a quality factor of the resonant oscillator, in particular below a resonance frequency of a LC tank circuit comprised in the resonant oscillator which maximizes a quality factor of the LC tank circuit.

公开(公告)号：US12075236B2

公开(公告)日：2024-08-27

申请号：US17655867

申请日：2022-03-22

Applicant: STMicroelectronics S.r.l.

Inventor： Francesco Caserta ,  Amedeo Veneroso

IPC: H04W12/03 ,  H04W8/18 ,  H04W12/041 ,  H04W12/0431

CPC classification number: H04W12/03 ,  H04W8/18 ,  H04W12/041 ,  H04W12/0431

Abstract: A method for concealing a subscription identifier at a user equipment including a mobile equipment and an integrated circuit card storing the subscription identifier, the method including receiving a corresponding request by a server to provide a corresponding subscription identifier, performing an elliptical curve encryption of the subscription identifier generating a concealed subscription identifier, the concealing operation including the mobile equipment sending an identity retrieve command to the card, performing, before receiving the identity retrieve command at the card, a pre-calculation of the ephemeral key pair including an ephemeral private key and ephemeral public key and the shared secret key, and in response to the respective state of completion indicating that completion of the computation of a valid ephemeral key pair or shared secret key, storing the corresponding values of the ephemeral key pair and shared secret key in a table in a memory of the card.

公开(公告)号：US12073860B2

公开(公告)日：2024-08-27

申请号：US18191639

申请日：2023-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Dario Livornesi ,  Alessio Emanuele Vergani ,  Paolo Pulici ,  Francesco Piscitelli ,  Enrico Mammei ,  Mojtaba Mohammadi Abdevand ,  Piero Malcovati ,  Edoardo Bonizzoni

IPC: G11B5/60 ,  H03F1/02

CPC classification number: G11B5/6029 ,  G11B5/607 ,  H03F1/0261

Abstract: According to an embodiment, a circuit includes a biasing and a low-frequency recovery circuit. The biasing circuit includes a voltage digital to analog converter (V-DAC), a differential difference amplifier coupled to the V-DAC, a common-mode feedback (CMFB) amplifier coupled to the differential difference amplifier, and a first pair of transistors arranged as a high-impedance structure and coupled to the differential difference amplifier and the CMFB amplifier. The low-frequency recovery circuit includes a current digital to analog converter (C-DAC), a second pair of transistors arranged as a high-impedance structure and coupled to the first pair of transistors, a pair of resistors having a resistance value equal to half a resistance of the resistive sensor, the pair of resistors arranged between the second pair of transistors and coupled to the C-DAC, and a gain circuit coupled to shared nodes between the second pair of transistors and the pair of resistors.

公开(公告)号：US12072372B2

公开(公告)日：2024-08-27

申请号：US17903344

申请日：2022-09-06

Applicant: STMicroelectronics S.r.l.

Inventor： Matteo Brivio ,  Nicola De Campo ,  Matteo Venturelli

IPC: G01R31/28

CPC classification number: G01R31/2834

Abstract: A system, method, and device to test an electronic circuit are disclosed having a stage to supply a driving signal to a load comprising a pull-up switch and a pull-down switch and a pre-driver stage including pre-driver circuits. The electronic circuit including circuits for testing the pre-driver stage under the control of an automatic testing equipment (ATE) to operate a built-in self-test sequence including test commands for the pre-driver stage under the control of an external test signal issued by the ATE. The system includes a time measuring circuit to measure duration of signals at the output of the stage coupled to a pass-fail check circuit, and to evaluate if the duration of signals at the output of the stage to determine whether the output satisfies a pass criterion.

公开(公告)号：US20240271935A1

公开(公告)日：2024-08-15

申请号：US18160723

申请日：2023-01-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alessandro MAGNANI ,  Matteo QUARTIROLI ,  Alessandra Maria RIZZO PIAZZA RONCORONI ,  Paolo ROSINGANA

IPC: G01C19/5776

CPC classification number: G01C19/5776 ,  G06F7/544 ,  H04R1/10 ,  H04R2460/13

Abstract: A device includes one or more inertial sensors and fusion circuitry coupled to the one or more inertial sensors. The inertial sensors, in operation, generate inertial sensor data with respect to a plurality of axes of movement. The fusion circuitry, in a polar fusion mode of operation, applies a plurality of polar rotation operations to the generated inertial sensor data to rotate the generated inertial sensor data onto an axis of the plurality of axes of movement. A fused data signal is generated based on a result of the plurality of polar rotation operations. The plurality of inertial sensors may include bone-conduction sensors.

公开(公告)号：US20240266459A1

公开(公告)日：2024-08-08

申请号：US18608301

申请日：2024-03-18

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Massimo Cataldo MAZZILLO ,  Valeria CINNERA MARTINO

IPC: H01L31/107 ,  H01L27/144 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/1075 ,  H01L27/1443 ,  H01L31/0352 ,  H01L31/18

Abstract: In at least one embodiment, a Geiger-mode avalanche photodiode, including a semiconductor body, is provided. The semiconductor body includes a semiconductive structure and a front epitaxial layer on the semiconductive structure. The front epitaxial layer has a first conductivity type. An anode region having a second conductivity type that is different from the first conductivity type extends into the front epitaxial layer. The photodiode further includes a plurality of gettering regions in the semiconductive structure.

公开(公告)号：US20240266259A1

公开(公告)日：2024-08-08

申请号：US18637906

申请日：2024-04-17

Applicant: STMicroelectronics S.r.l.

Inventor： Mauro MAZZOLA ,  Matteo DE SANTA

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/4951 ,  H01L21/50 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/74

Abstract: In providing electrical wire-like connections between at least one semiconductor die arranged on a semiconductor die mounting area of a substrate and an array of electrically-conductive leads in the substrate, pressure force is applied to the electrically-conductive leads in the substrate during bonding the wire-like connections to the electrically-conductive leads. Such a pressure force is applied to the electrically-conductive leads in the substrate via a pair of mutually co-operating force transmitting surfaces. These surfaces include a first convex surface engaging a second concave surface.

公开(公告)号：US12057474B2

公开(公告)日：2024-08-06

申请号：US17325932

申请日：2021-05-20

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Antonino Schillaci ,  Paola Maria Ponzio ,  Roberto Cammarata

IPC: H03F3/195 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H03F3/217

CPC classification number: H01L29/0634 ,  H01L29/66712 ,  H01L29/7811 ,  H03F3/2176 ,  H03F2200/451

Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.

公开(公告)号：US12057180B2

公开(公告)日：2024-08-06

申请号：US17934102

申请日：2022-09-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Antonino Conte ,  Francois Maugain

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/30 ,  H10B41/40

CPC classification number: G11C16/3445 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  H10B41/30 ,  H10B41/40

Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

公开(公告)号：US12051731B2

公开(公告)日：2024-07-30

申请号：US17698986

申请日：2022-03-18

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Patrick Fiorenza ,  Fabrizio Roccaforte ,  Mario Giuseppe Saggio

IPC: H01L29/16 ,  H01L27/06 ,  H01L29/423 ,  H01L29/872

CPC classification number: H01L29/4234 ,  H01L27/0629 ,  H01L29/1608 ,  H01L29/872

Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.