公开(公告)号：US20250102593A1

公开(公告)日：2025-03-27

申请号：US18472684

申请日：2023-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Francesco Rundo ,  Michele Calabretta ,  Marco Maria Branciforte ,  Concetto Spampinato ,  Salvatore Coffa

IPC: G01R31/40 ,  G06N3/084

Abstract: A method of characterizing a parameter (e.g., threshold voltage) of a power electronic device using an artificial intelligence (AI) model includes sampling measured parameter values (e.g., voltage, current) of the power electronic device during operation and characterizing the parameter of the power electronic device using the AI model in inference mode with the measured parameter values as inputs. The AI model is trained using a joint loss function including a Jacobian regularization term. The Jacobian regularization term may depend on the norm of at least one Jacobian of a corresponding set of training inputs. A power electronics system configured to perform the method includes the power electronic device and a computing system with a processor and memory storing the AI model. The computing system may be a microcontroller. The system may also include an analog-to-digital converter (ADC) circuit, such as in the microcontroller.

公开(公告)号：US20250095731A1

公开(公告)日：2025-03-20

申请号：US18824446

申请日：2024-09-04

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Antonino CONTE ,  Francesco TOMAIUOLO ,  Jeremie Clement JASSE ,  Anna GANDOLFO

IPC: G11C13/00

Abstract: A method of operating phase change memories and corresponding device and computer program product are provided. An example of write operations in a phase change memory includes: if a first set contains at least one cell set at a high logic level, performing a reset write operation to set to a low logic level the cell by applying at least one current reset pulse; and if a second set contains at least one cell set at a low logic level, performing a set write operation to set to a high logic level the afore the cell. Success or failure of the set write operation is verified. Success or failure of the reset write operation is verified. The write operation is considered as failed in response to the reset write operation being considered as failed or to the set write operation being considered as failed.

公开(公告)号：US20250088104A1

公开(公告)日：2025-03-13

申请号：US18463753

申请日：2023-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Sandro Rossi ,  Niccolò Brambilla ,  Francesco Franco

IPC: H02M3/158 ,  H02M1/088

Abstract: A Buck converter includes: a first power switch coupled between a supply voltage node and a switching node, where the first power switch is configure to be controlled by a first control signal; a boot-strap capacitor, where a first terminal of the boot-strap capacitor is coupled to the switching node; a first buffer coupled between a first node and a control terminal of the first power switch; a first switch circuit coupled between the first node and a second terminal of the boot-strap capacitor, where the first switch circuit is controlled by the first control signal, and is configured to pass through a first charging current provided by the boot-strap capacitor when the first control signal is asserted; and a slew-rate control capacitor, where a first terminal of the slew-rate control capacitor is coupled to the first node.

公开(公告)号：US20250088090A1

公开(公告)日：2025-03-13

申请号：US18829765

申请日：2024-09-10

Applicant: STMicroelectronics International N.V.

Inventor： Alessandro BERTOLINI ,  Germano NICOLLINI ,  Alessandro GASPARINI ,  Alberto BRUNERO ,  Alberto CATTANI

IPC: H02M1/088 ,  H02M3/158

Abstract: A time-based DC-DC converter is controlled in response to a first oscillator signal based on a first control signal, a second oscillator signal based on a second control signal and a controlled current based on a feedback control signal. The first control signal and the second control signal are a function of the controlled current. The feedback control signal is generated as a function of the first and second oscillator signals by: generating at least two binary signals including a first binary signal based on a difference between the first oscillator signal and the reference signal and a second binary signal based on a difference between the second oscillator signal and the reference signal; and generating via a charge pump the feedback control signal based on the first binary signal and the second binary signal.

公开(公告)号：US20250087605A1

公开(公告)日：2025-03-13

申请号：US18784674

申请日：2024-07-25

Applicant: STMicroelectronics International N.V.

Inventor： Antoine Le Ravallec ,  David Gaidioz ,  Christophe Arricastres

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

Abstract: The present description concerns a device adapted to transmitting and receiving signals with a same antenna, comprising first, second, and third windings, the first and second windings being coupled so as to transmit the signals to be transmitted by the antenna, the first and third windings being coupled so as to transmit the signals received by the antenna, the device comprising first and second chips, the first chip comprising the antenna and the first winding, and the second chip comprising a winding from among the second and third windings, the first and second chips being bonded to each other by molecular bonding.

公开(公告)号：US20250085794A1

公开(公告)日：2025-03-13

申请号：US18752451

申请日：2024-06-24

Applicant: STMicroelectronics International N.V.

Inventor： Bowei Chen

IPC: G06F3/0354 ,  G06F3/044 ,  G06F3/04883

Abstract: A display processing method includes collecting raw data of a contact with a stylus on a touch screen by scanning the touch screen with a touch controller. The method further includes normalizing the raw data to determine normalized data, and receiving related information associated with the contact from the stylus. And the method further includes transmitting the related information associated with the contact and transmitting the normalized data.

公开(公告)号：US20250085314A1

公开(公告)日：2025-03-13

申请号：US18367044

申请日：2023-09-12

Applicant: STMicroelectronics International N.V.

Inventor： Francesco BORGIOLI ,  Roberto Pio BAORDA ,  Paolo ANGELINI ,  Danilo Karim KADDOURI ,  Lorenzo ERCOLINI

IPC: G01R15/20 ,  G01R19/10

Abstract: Disclosed herein is a system for measuring current, including an input inductor and a self-test inductor through which respective input and self-test currents flow. A Hall-effect sensor circuit senses magnetic fields around these inductors, producing differential voltage outputs. These outputs are received by an input and self-test extraction circuit, which alternatingly outputs differential voltages representative of the magnetic fields around the inductors. Amplification of these differential voltages is performed by an amplifier. Sampling of the amplified differential voltages is performed by two sample/hold circuits, each designated for a specific inductor's magnetic field. An integrator circuit adjusts a voltage for the Hall effect sensor circuit, causing the gain applied to the sampled differential voltage to remain consistent and uninfluenced by the sensitivity of the Hall effect sensor circuit.

公开(公告)号：US12249644B2

公开(公告)日：2025-03-11

申请号：US17058117

申请日：2019-05-07

Applicant: STMicroelectronics International N.V.

Inventor： Matthieu Nongaillard ,  Thomas Oheix

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20

Abstract: An enhancement-mode high-electron-mobility transistor comprises a structure including a stack made of III-V semiconductor materials defining an interface and capable of forming a conduction layer in the form of a two-dimensional electron gas layer; a source electrode and a drain electrode forming an electrical contact with the conduction layer; and a gate electrode arranged on top of the structure, between the source electrode and the drain electrode. The structure comprises a bar that is arranged below the gate electrode and passes through the interface of the stack. The bar comprises two semiconductor portions exhibiting opposite types of doping, defining a p-n junction in proximity to the interface.

公开(公告)号：US20250081644A1

公开(公告)日：2025-03-06

申请号：US18814251

申请日：2024-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Tarek LULE

IPC: H01L27/146 ,  H04N25/77 ,  H04N25/78

Abstract: The present disclosure relates to an image sensor comprising an array of pixels arranged in first rows and in first columns. The pixels are arranged in groups of N*N pixels, with N an integer equal to or higher than 2. In each group, the pixels of the group are distributed into one or more sub-groups of a plurality of pixels. Each pixel comprises: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of a same sub-group, and coupled to a first potential, a first transistor coupling the first and second nodes to each other, a second source-follower transistor having a gate connected to the first node, and a third transistor coupling the source of the third transistor to a reading line.

公开(公告)号：US20250081494A1

公开(公告)日：2025-03-06

申请号：US18458877

申请日：2023-08-30

Applicant: STMicroelectronics International N.V.

Inventor： Arnaud YVON

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A process forms a high electron mobility transistor (HEMT) device with a recessed gate without damaging sensitive areas of the HEMT device. The process utilizes a first epitaxial growth process to grow a first set of layers of the HEMT. The epitaxial growth process is then stopped and a passivation layer is formed on the first set of layers. The passivation layer is then patterned to provide a passivation structure at a desired location of the recessed gate electrode. The channel layer and one or more barrier layers are then formed in a second epitaxial growth process in the presence of the passivation structure. The result is that the channel layer and the barrier layer growth around the passivation structure. The passivation structure is then removed, effectively leaving a recess in the channel layer. The gate electrode is then formed in the recess.