公开(公告)号：EP1298935A2

公开(公告)日：2003-04-02

申请号：EP02292260.3

申请日：2002-09-16

Applicant: STMicroelectronics S.A. ,  Groupe des Ecoles des Telecommunications ,  STMicroelectronics Pte Ltd.

Inventor： Bard, Jean-Michel ,  Danger, Jean-Luc ,  Hui, Lucas ,  Cunat, Christophe

IPC: H04N7/30

CPC classification number: H04N19/436 ,  H04N19/126 ,  H04N19/152 ,  H04N19/176 ,  H04N19/194 ,  H04N19/196 ,  H04N19/197 ,  H04N19/60

Abstract: Procédé de compression d'un signal d'image numérique dans lequel un premier jeu de pas de quantification, unique pour un segment donné, est déterminé pour que le nombre de bits nécessaires pour coder les données quantifiées correspondant à ce segment soit supérieur à une valeur cible. Ce premier jeu de pas de quantification étant ensuite modifié, en priorité, pour les blocs du segment pour lesquels le gain, au cours de cette modification, sur la réduction du nombre de bits nécessaires pour coder les données quantifiées correspondant au segment auquel il appartient, est le plus élevé. Cette modification est effectuée, sur autant de blocs qu'il est nécessaire pour que le nombre de bits de ce segment soit inférieur ou égal à la valeur cible.
Dispositif pour la mise en oeuvre de ce procédé.

Abstract translation: 该方法包括形成在像素处分配的系数的空间块，将每个块变换成频域，将一组频率块与宏块的关联以及一组宏块分成多个段，并执行两个步骤 每个细分的量化。 每个频率块的系数的第一次量化对于宏块的所有频率块具有相同的索引。 至少部分频率块的系数的第二量化是用第一定量步骤代替第一定量步骤的第二组量化步骤。 这两组量化步骤一方面被选择作为表示段的量化系数所需的数据量的目标值（VC）的函数，另一方面选择为 段的频率块。 相对于块的增益因子表示在从一组定量步骤到块的另一组经过时所需的数据量的减少。 宏块的所有频率块的相同索引对于段的所有宏块也是相同的。 选择第一组量化步骤，使得表示每个数据段的量化系数的数据量高于目标值。 第二组量化步骤比第一组粗; 数据量小于或等于目标值，并且对于增益因子较高的段的频率块优先进行量化，并且对于段的至少另一个频率块以递减增益重复 只要数据量高于目标值即可。 为频率块计算的增益因子是用于表示频率块与第一组和第二组的量化系数所需的数据量之间的差，除以用于表示量化的能力所需的数据量与 第一套。 第一量化包括并行的三个处理，每个处理包括量化，编码和计算表示段的量化数据所需的数据量的操作。 通过使用将参数（QID）初始化为零（120）的算法来进行量化，计算压缩数据的长度（LS）（130），如果长度（LS）小于 或等于目标值（VC）（140）; 在测试为负的情况下，参数（QID）增加单位（150），重复计算; 操作（130,140,​​150）对应于第一次量化; 如果测试是肯定的，测试（160）验证参数（QID）是否等于零; 如果确实如此，数据不能被压缩，不需要进一步的处理; 如果测试是否定的，则减小一个参数（QID）的值与段（170）的所有块相关联，则以降低质量因子的顺序执行块的置换（sigma）（180） index（j）被初始化为零，参数按单位（200）递增，计算长度（LS）（210），如果长度（LS）小于或等于 目标值（VC）; 如果测试为负，则索引（j）增加单位（230）; 操作（200,210,220,230,240）对应于第二次量化。 声明实现该方法的设备。

公开(公告)号：EP1119910A1

公开(公告)日：2001-08-01

申请号：EP98950602.7

申请日：1998-10-13

Applicant: STMicroelectronics Pte Ltd. ,  STMicroelectronics Limited

Inventor： MALIK, Rakesh-STMicroelectronics Limited ,  GOEL, Puneet

IPC: H03H17/02

CPC classification number: H03H17/0223 ,  H03H17/0225 ,  H03H17/0227 ,  H03H2218/08 ,  H03H2218/10

Abstract: The invention relates to area efficient realization of coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines CLin_0, CLin_1.....CLin_n and BLin_0, BLin_1,....BLin_n coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The invention also gives the area minimal realization of digital filters based on coefficient block [A], when operated in bit serial fashion. The optimization techniques and structure of the present invention are good for bit-serial digital filters typically a finite impulse response (FIR) filter, infinite impulse response filter (IIR) and for other filters and applications based on combinational logic consisting of delay element (T), multiplier (M), serial adder (SA) and serial subtractor (SS).

公开(公告)号：EP0603436B1

公开(公告)日：1999-03-03

申请号：EP92311665.1

申请日：1992-12-21

Applicant: STMicroelectronics Pte Ltd.

Inventor： Jo, Sung Jin

IPC: H04M3/00 ,  H04M3/22 ,  H04M1/00

CPC classification number: H04M1/80 ,  H04M3/2272 ,  H04M3/4283

公开(公告)号：US12266636B2

公开(公告)日：2025-04-01

申请号：US17556547

申请日：2021-12-20

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En Luan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: The present disclosure is directed to a package that includes a plurality of die that are stacked on each other. The plurality of die are within a first resin and conductive layer is on the first resin. The conductive layer is coupled between ones of first conductive vias extending into the first resin to corresponding ones of the plurality of die. The conductive layer and the first conductive vias couple ones of the plurality of die to each other. A second conductive via extends into the first resin to a contact pad of the substrate, and the conductive layer is coupled to the second conductive via coupling ones of the plurality of die to the contact pad of the substrate. A second resin is on and covers the first resin and the conductive layer on the first resin. In some embodiments, the first resin includes a plurality of steps (e.g., a stepped structure). In some embodiments, the first resin includes inclined surfaces (e.g., sloped surfaces).

公开(公告)号：US12136608B2

公开(公告)日：2024-11-05

申请号：US18166931

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Yong Chen ,  David Gani

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/16

Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

公开(公告)号：US11848378B2

公开(公告)日：2023-12-19

申请号：US17373198

申请日：2021-07-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Ditto Adnan ,  Maurizio Gabriele Castorina ,  Voon Cheng Ngwan ,  Fadhillawati Tahir

IPC: H01L29/78 ,  H01L21/765 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/765 ,  H01L29/401 ,  H01L29/407 ,  H01L29/66734

Abstract: A semiconductor substrate has a trench extending from a front surface and including a lower part and an upper part. A first insulation layer lines the lower part of the trench, and a first conductive material in the lower part is insulated from the semiconductor substrate by the first insulating layer to form a field plate electrode of a transistor. A second insulating layer lines sidewalls of the upper part of said trench. A third insulating layer lines a top surface of the first conductive material at a bottom of the upper part of the trench. A second conductive material fills the upper part of the trench. The second conductive material forms a gate electrode of the transistor that is insulated from the semiconductor substrate by the second insulating layer and further insulated from the first conductive material by the third insulating layer.

公开(公告)号：US11774422B2

公开(公告)日：2023-10-03

申请号：US16458561

申请日：2019-07-01

Applicant: STMicroelectronics PTE LTD

Inventor： Fangxing Yuan ,  Ravi Shankar ,  Olivier Le Neel

IPC: G01N33/00 ,  G01N29/22

CPC classification number: G01N33/0013 ,  G01N29/228 ,  G01N33/0016 ,  G01N33/0031

Abstract: The present disclosure is directed to a selective multi-gas sensor device that detects when a high concentration level of a particular gas, such as methane, carbon monoxide, and/or ethanol, is present. The selective multi-gas sensor device detects and identifies a particular gas based on a ratio between a sensitivity of a gas sensitive material at a first temperature and a sensitivity of the gas sensitive material at a second temperature.

公开(公告)号：US20230268421A1

公开(公告)日：2023-08-24

申请号：US18168509

申请日：2023-02-13

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS PTE LTD

Inventor： Vincenzo ENEA ,  Voon Cheng NGWAN

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/66734 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/7813 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66727

Abstract: A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).

公开(公告)号：US20230197545A1

公开(公告)日：2023-06-22

申请号：US18166922

申请日：2023-02-09

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/293 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3178 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0655 ,  H01L2224/02371

Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

公开(公告)号：US11502029B2

公开(公告)日：2022-11-15

申请号：US16927776

申请日：2020-07-13

Applicant: STMICROELECTRONICS PTE LTD ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Laurent Herard ,  David Parker ,  David Gani

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/3065

Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.