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1.发明公开AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119909A1
公开(公告)日：2001-08-01
申请号：EP98950601.9
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
Inventor： MALIK, Rakesh,STMicroelectronics Limited , GOEL, Puneet
IPC: H03H17/02
CPC classification number: H03H17/0225
Abstract: The invention relates to area efficient realization of coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines CLin_0, CLin_1...CLin_n and BLin_0, BLin_1,... BLin_n coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The invention also gives the area minimal realization of digital filters based on coefficient block [A], when operated in bit serial fashion. The optimization techniques and structure of the present invention are good for linear digital filters typically a finite impulse response (FIR) filter, infinite impulse response filter (IIR) and for other filters and applications based on combinational logic consisting of delay element (T), multiplier (M), adder (SA) and subtractor (SS).
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2.发明授权AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119910B1
公开(公告)日：2004-01-14
申请号：EP98950602.7
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
Inventor： MALIK, Rakesh-STMicroelectronics Limited , GOEL, Puneet
IPC: H03H17/02
CPC classification number: H03H17/0223 , H03H17/0225 , H03H17/0227 , H03H2218/08 , H03H2218/10
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3.发明授权AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119909B1
公开(公告)日：2004-01-14
申请号：EP98950601.9
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
IPC: H03H17/02
CPC classification number: H03H17/0225
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4.发明公开AREA EFFICIENT REALIZATION OF COEFFICIENT ARCHITECTURE FOR BIT-SERIAL FIR, IIR FILTERS AND COMBINATIONAL/SEQUENTIAL LOGIC STRUCTURE WITH ZERO LATENCY CLOCK OUTPUT 有权FOR BIT SERIAL FIR，IIR滤波器和组合/顺序逻辑结构无延迟系数建筑面积高效生产
公开(公告)号：EP1119910A1
公开(公告)日：2001-08-01
申请号：EP98950602.7
申请日：1998-10-13
Applicant: STMicroelectronics Pte Ltd. , STMicroelectronics Limited
Inventor： MALIK, Rakesh-STMicroelectronics Limited , GOEL, Puneet
IPC: H03H17/02
CPC classification number: H03H17/0223 , H03H17/0225 , H03H17/0227 , H03H2218/08 , H03H2218/10
Abstract: The invention relates to area efficient realization of coefficient block [A] or architecture [A] with hardware sharing techniques and optimizations applied to this block. The block [A] is connected to coefficient lines CLin_0, CLin_1.....CLin_n and BLin_0, BLin_1,....BLin_n coming from block [E] and/or [F], to be connected to perform filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The invention also gives the area minimal realization of digital filters based on coefficient block [A], when operated in bit serial fashion. The optimization techniques and structure of the present invention are good for bit-serial digital filters typically a finite impulse response (FIR) filter, infinite impulse response filter (IIR) and for other filters and applications based on combinational logic consisting of delay element (T), multiplier (M), serial adder (SA) and serial subtractor (SS).
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