公开(公告)号：US20140126031A1

公开(公告)日：2014-05-08

申请号：US14070732

申请日：2013-11-04

Applicant: ASIA PACIFIC MICROSYSTEMS, INC.

Inventor： Jer-Wei Hsieh ,  Han-Tang Su

IPC: B81C1/00 ,  G02B26/08

CPC classification number: B81C1/00603 ,  B81B2201/042 ,  B81B2203/0136 ,  B81C1/0015 ,  G02B26/0833

Abstract: In a method for fabricating a self-aligned vertical comb drive structure, a multi-layer structure is first formed. The multi-layer structure includes inter-digitated first and second comb structures formed via etching using a first mask layer as a mask. The first comb structure includes a plurality of first comb fingers, each having a first finger portion formed in a first device layer and a second finger portion formed in a second device layer and separated from the first finger portion by a self-aligned pattern on a stop layer. The second comb structure includes a plurality of second comb fingers formed solely in the second device layer. The second finger portions of the first comb fingers are subsequently removed.

Abstract translation: 在制造自对准垂直梳状驱动结构的方法中，首先形成多层结构。 多层结构包括使用第一掩模层作为掩模通过蚀刻形成的经数字化的第一和第二梳状结构。 第一梳结构包括多个第一梳指，每个第一梳指具有形成在第一器件层中的第一指部和形成在第二器件层中的第二指部，并且在第一器件层上分离自对准图案 停止层。 第二梳结构包括仅在第二器件层中形成的多个第二梳指。 随后去除第一梳齿的第二手指部分。

公开(公告)号：US20040063039A1

公开(公告)日：2004-04-01

申请号：US10464495

申请日：2003-06-19

Applicant: ASIA PACIFIC MICROSYSTEMS, INC.

Inventor： Shang-Yu Liang ,  Shu-Hui Tsai ,  Chun-Hsien Lee ,  Chung-Hsien Lin

IPC: G03F007/16 ,  G03F007/20 ,  G03F007/40

CPC classification number: H01L23/645 ,  H01F17/0013 ,  H01F41/045 ,  H01F2017/0046 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: Disclosed herein is a method for inductor An Improved Structure For the Endpiece of Tape Rule of the high frequency integrated passive devices in which a spiral inductor pattern is formed on an insulation substrate, the spiral inductor pattern is spirally coiled outwards from the center. A thick film dielectric layer made of bisbenzocyclobutene (BCB) is formed on the spiral inductor pattern. A metal layer can be formed according to under bump metallization technique (UBM). The metal layer is either formed into a continuous spirally coiled form or a spread discrete configuration. With this structure, laser trimming can be applied to the metal layer pattern so as to acquire an ideal inductance value, thereby achieving wafer level trimming and compensating the process tolerance.

Abstract translation: 这里公开了一种电感器的方法。在绝缘基板上形成有螺旋形电感器图案的高频集成无源器件的带状端子规则的改进结构中，螺旋形电感器图案从中心向外螺旋地卷绕。 在螺旋电感图案上形成由双苯并环丁烯（BCB）制成的厚膜电介质层。 可以根据凸块下金属化技术（UBM）形成金属层。 金属层或者形成为连续的螺旋卷曲形式或扩展的离散构造。 利用该结构，可以对金属层图案施加激光微调，以获得理想的电感值，从而实现晶片级修整并补偿工艺公差。

公开(公告)号：US20030205948A1

公开(公告)日：2003-11-06

申请号：US10253861

申请日：2002-09-25

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Chung-Hsien Lin ,  Shu-Hui Tsai ,  Chen-Hsun Du ,  Ruey-Shing Huang

IPC: H01L041/08

CPC classification number: H03H3/04 ,  H03H9/542 ,  H03H2003/0071 ,  H03H2003/0464

Abstract: A film bulk acoustic device having integrated trimmable device comprises a FBAR and a integrated tunable and trimmable device being integrated on a common substrate, at least a common electrode or piezoelectric layer. By trimming the integrated trimmable device or the FBAR and alter either the capacitance or inductance of the integrated trimmable device until the film bulk acoustic device having integrated trimmable device achieves the target resonance frequency. By taking advantage of the electrostatic force, the integrated tunable device is capable of providing tuning until the film bulk acoustic device having integrated tunable device achieves the target resonance frequency.

Abstract translation: 具有集成可调整装置的胶片体音响装置包括一个FBAR和集成的可调和可调整装置，其集成在共同的基板上，至少是公共电极或压电层。 通过修整集成可调整装置或FBAR，并改变集成可调整装置的电容或电感，直到具有集成可调整装置的胶片体声装置达到目标共振频率。 通过利用静电力，集成的可调谐装置能够提供调谐，直到具有集成的可调谐装置的膜体音响装置达到目标共振频率。

公开(公告)号：US20020189062A1

公开(公告)日：2002-12-19

申请号：US10134369

申请日：2002-04-30

Applicant: ASIA PACIFIC MICROSYSTEMS, INC.

Inventor： Chung-Hsien Lin ,  Ju-Mei Lu ,  Shu-Hui Tsai ,  Chenkuo Lee

IPC: H04R017/00 ,  H05K003/02

CPC classification number: H03H3/02 ,  H04R17/00 ,  Y10T29/42 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A manufacturing method for a high quality film bulk acoustic wave device, wherein a lower electrode protecting layer is partially defined or not applied, thus the quality factor of the bulk acoustic wave device is improved.

Abstract translation: 一种用于高质量薄膜压电元件的制造方法，其中部分限定或不施加下电极保护层，从而提高了体声波器件的品质因数。

公开(公告)号：US09553055B2

公开(公告)日：2017-01-24

申请号：US14922334

申请日：2015-10-26

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Lin Yin

IPC: H01L23/00 ,  H01L21/283 ,  H01L21/762 ,  B06B1/02 ,  H01L21/306

CPC classification number: H01L23/562 ,  B06B1/0292 ,  B81C1/00 ,  H01L21/283 ,  H01L21/306 ,  H01L21/762 ,  H01L21/76251 ,  H01L23/00 ,  H01L24/03 ,  H01L24/84 ,  H01L24/95 ,  H01L2224/37599 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/37099

Abstract: The present disclosure provides a method for fabricating semiconductor devices having reinforcing elements. The method includes steps of providing a first wafer having a lower electrode layer and an insulation layer; forming a device layer; etching the device layer and the insulation layer to form recesses; etching the device layer to form separation trenches and upper electrodes; forming reinforcing elements; and depositing metal pads. The reinforcing elements strengthen the integration of the upper electrodes and the insulation layer.

Abstract translation: 本公开提供了一种制造具有增强元件的半导体器件的方法。 该方法包括提供具有下电极层和绝缘层的第一晶片的步骤; 形成器件层; 蚀刻器件层和绝缘层以形成凹陷; 蚀刻器件层以形成分离沟槽和上电极; 形成增强元件; 并沉积金属垫。 增强元件加强了上电极和绝缘层的集成。

公开(公告)号：US09459172B2

公开(公告)日：2016-10-04

申请号：US14520550

申请日：2014-10-22

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Ming-Yan Chen

IPC: G01L9/06 ,  G01L19/06 ,  G01L9/00

CPC classification number: G01L19/0618 ,  G01L9/0052 ,  G01L9/0054 ,  G01L9/0055

Abstract: A diaphragm piezoresistive pressure sensor includes: a base member; a diaphragm including a middle portion and a surrounding portion surrounding the middle portion; a spacer disposed between and cooperating with the base member and the diaphragm to define a cavity thereamong; an inner abutment member disposed in the cavity and spaced apart from the base member by a clearance; and a piezoresistive sensor unit embedded in the diaphragm. The spacer surrounds and is spaced apart from the inner abutment member. At least one of the inner abutment member and the middle portion of the diaphragm defines a chamber therebetween.

Abstract translation: 隔膜压阻式压力传感器包括：基座构件; 隔膜，包括中间部分和围绕中间部分的周围部分; 间隔件，其设置在所述基座构件和所述隔膜之间并与所述隔膜配合以在其中限定空腔; 内部邻接构件，其设置在所述空腔中并与所述基座构件间隔开间隙; 以及嵌入隔膜中的压阻传感器单元。 间隔件围绕并与内邻接构件间隔开。 隔膜的至少一个内邻接构件和中间部分在它们之间形成一个室。

公开(公告)号：US20160244323A1

公开(公告)日：2016-08-25

申请号：US15144896

申请日：2016-05-03

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Jerwei Hsieh

IPC: B81B7/00

CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

Abstract: An integrated MEMS device is provided. The integrated MEMS device comprises a circuit chip and a device chip. The circuit chip has a patterned first bonding layer disposed thereon, the bonding layer being composed of a conductive material/materials. The device chip has a first structural layer and a second structural layer, the first structural layer being connected to the second structural layer and the first bonding layer of the circuit chip, and being sandwiched between the second structural layer and the circuit chip. A plurality of hermetic spaces are enclosed by the first structural layer, the second structural layer, the first bonding layer and the circuit chip.

Abstract translation: 提供集成的MEMS器件。 集成MEMS器件包括电路芯片和器件芯片。 电路芯片具有设置在其上的图案化第一接合层，接合层由导电材料/材料构成。 器件芯片具有第一结构层和第二结构层，第一结构层连接到电路芯片的第二结构层和第一结合层，并夹在第二结构层和电路芯片之间。 第一结构层，第二结构层，第一结合层和电路芯片包围多个封闭空间。

公开(公告)号：US09359193B2

公开(公告)日：2016-06-07

申请号：US14165752

申请日：2014-01-28

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Jerwei Hsieh

IPC: H01L21/4763 ,  B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

Abstract: An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.

Abstract translation: 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。

公开(公告)号：US20150274514A1

公开(公告)日：2015-10-01

申请号：US14165752

申请日：2014-01-28

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Jerwei Hsieh

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0038 ,  B81B7/0058 ,  B81B2201/032 ,  B81C1/00238 ,  B81C1/00817 ,  B81C1/00825 ,  B81C2201/053 ,  B81C2201/056 ,  B81C2203/0785

Abstract: An integrated MEMS device and its manufacturing method are provided. In the manufacturing method, the sacrificial layer is used to integrate the MEMS wafer and the circuit wafer. The advantage of the present invention comprises preventing films on the circuit wafer from being damaged during process. By the manufacturing method, a mechanically and thermally stable structure material, for example: monocrystalline silicon and polysilicon, can be used. The integrated MEMS device manufactured can also possess the merit of planar top-surface topography with high fill factor. The manufacturing method is especially suitable for manufacturing MEMS array device.

Abstract translation: 提供集成的MEMS器件及其制造方法。 在制造方法中，牺牲层用于集成MEMS晶片和电路晶片。 本发明的优点包括防止电路晶片上的膜在加工过程中被损坏。 通过制造方法，可以使用机械和热稳定的结构材料，例如：单晶硅和多晶硅。 制造的集成MEMS器件也可以具有高填充因子的平面顶表面形貌的优点。 该制造方法特别适用于制造MEMS阵列器件。

公开(公告)号：US20040183150A1

公开(公告)日：2004-09-23

申请号：US10390628

申请日：2003-03-19

Applicant: Asia Pacific Microsystems, Inc.

Inventor： Hung-Dar Wang ,  Shih-Chin Gong

IPC: H01L029/82

CPC classification number: G01L9/0054

Abstract: The present invention relates to a silicon pressure sensor that in need of three strips of piezoresistors on each side and the manufacturing method thereof; wherein, the impurity concentration of the piezoresistors are about 1019-1020 cmnull3 in order to reduce the influence of temperature; the lead between the piezoresistors (namely the internal connection lead) is a highly-doping interconnect (about 1021 cmnull3) fabricated along the direction with minimum piezoresistance coefficient; with regard to the connection circuit for connecting the piezoresistors with the external Wheatstone bridge circuit (namely the external connection circuit), of which one end near the inner side of the membrane is also fabricated along the direction with minimum piezoresistance coefficient, and another end of the lead near the edge of the membrane is a interconnect that is perpendicular to the diaphragm, and is connected out to the external circuit; with this structure, the four resistors of the Whetstone bridge are balanced and symmetrized, thus the zero offset caused by the variations in resistance of the bridge can be reduced in order to simplify the signal-processing circuit.

Abstract translation: 硅压力传感器及其制造方法技术领域本发明涉及一种硅压力传感器及其制造方法，所述硅压力传感器在每侧需要三条压敏电阻片; 其中为了降低温度的影响，压敏电阻的杂质浓度为约10〜10 20 cm -3 -3。 压敏电阻器之间的引线（即内部连接引线）是沿着具有最小压阻系数的方向制造的高度掺杂的互连（约10 21 cm -3）; 关于将压电电阻与外部惠斯通电桥电路（即外部连接电路）连接的连接电路，其膜的内侧附近的一端也沿着具有最小压阻系数的方向制造，另一端 膜边缘附近的引线是与隔膜垂直的互连线，并连接到外部电路; 通过这种结构，Whetstone桥的四个电阻器被平衡和对称化，因此可以减小由桥的电阻变化引起的零点偏移，以简化信号处理电路。