公开(公告)号：US20030012052A1

公开(公告)日：2003-01-16

申请号：US10223488

申请日：2002-08-20

Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.

Inventor： Nozomu Matsuzaki ,  Kazuyoshi Shiba ,  Yasuhiro Taniguchi ,  Toshihiro Tanaka ,  Yutaka Shinagawa

IPC: G11C011/34

CPC classification number: G11C16/3409 ,  G11C8/08 ,  G11C16/12 ,  G11C16/3404

Abstract: A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.

公开(公告)号：US20020199056A1

公开(公告)日：2002-12-26

申请号：US10163364

申请日：2002-06-07

Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.

Inventor： Kazushige Ayukawa ,  Seiji Miura ,  Tetsuya Iwamura ,  Kouichi Hoshi ,  Yoshikazu Saitou

IPC: G06F012/00

CPC classification number: G11C11/4087 ,  G11C11/005 ,  G11C11/406 ,  G11C2207/2245 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/06135 ,  H01L2224/06156 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

Abstract translation: 非易失性存储器，SRAM，DRAM和控制电路被模块化成单个封装。 控制电路将地址分配给SRAM，并将DRAM的地址分配给SRAM，并将需要长时间保持的数据保存在SRAM中。 DRAM的两个芯片映射到相同的地址空间并交替刷新。 多个芯片被布置为使得它们相互层压，并且它们通过BGA或芯片间接合来布线。

公开(公告)号：US20140198577A1

公开(公告)日：2014-07-17

申请号：US14214969

申请日：2014-03-16

Applicant: HITACHI ULSI SYSTEMS CO., LTD. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiro TANAKA ,  Yukiko UMEMOTO ,  Mitsuru HIRAKI ,  Yutaka SHINAGAWA ,  Masamichi FUJITO ,  Kazufumi SUZUKAWA ,  Hiroyuki TANIKAWA ,  Takashi YAMAKI ,  Yoshiaki KAMIGAKI ,  Shinichi MINAMI ,  Kozo KATAYAMA ,  Nozomu MATSUZAKI

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US08782300B2

公开(公告)日：2014-07-15

申请号：US13692506

申请日：2012-12-03

Applicant: Hitachi ULSI Systems Co., Ltd.

Inventor： Ayumi Hiromatsu ,  Masahiro Katayama ,  Takanaga Yamazaki

IPC: G06F3/00 ,  G06F13/00 ,  G06F15/16

CPC classification number: G06F12/0246 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0262 ,  H04L25/38

Abstract: An electronic apparatus provided with a serial communication circuit achieving a baud rate adjustment with high precision is provided. For example, a bit width of each of a plurality of bits in received serial data is measured by a clock counter, and an average value of the bit width is calculated detecting its maximum value and minimum value. Moreover, for example, a maximum tolerance and a minimum tolerance are calculated as a value substantially 1.5 times the average value and a value substantially 0.5 times the average value, and determination is made as to whether or not the maximum value and the minimum value are within a range between the maximum tolerance and the minimum tolerance. If they are within the range, the corresponding average value is set in a baud rate setting register.

Abstract translation: 提供了具有实现高精度的波特率调整的串行通信电路的电子设备。 例如，通过时钟计数器测量接收到的串行数据中的多个比特的比特宽度，并且计算其宽度的平均值来检测其最大值和最小值。 此外，例如，最大公差和最小公差被计算为基本上为平均值的1.5倍的值和基本上为平均值的0.5倍的值，并且确定最大值和最小值是否为 在最大公差和最小公差之间的范围内。 如果它们在范围内，则在波特率设置寄存器中设置相应的平均值。

公开(公告)号：US20140099770A1

公开(公告)日：2014-04-10

申请号：US14100429

申请日：2013-12-09

Applicant: Hitachi ULSI Systems Co., Ltd. ,  Renesas Electronics Corporation

Inventor： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC: H01L21/74 ,  H01L21/762

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

Abstract translation: 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US08604505B2

公开(公告)日：2013-12-10

申请号：US13858274

申请日：2013-04-08

Applicant: Renesas Electronics Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC: H01L33/00

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

公开(公告)号：US20130241029A1

公开(公告)日：2013-09-19

申请号：US13858274

申请日：2013-04-08

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Kenichi KURODA ,  Kozo WATANABE ,  Hirohiko YAMAMOTO

IPC: H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

Abstract translation: 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US20040189842A1

公开(公告)日：2004-09-30

申请号：US10816925

申请日：2004-04-05

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd. ,  Hitachi Tohbu Semiconductor, Ltd.

Inventor： Yasutoshi Aibara ,  Hiroki Nakajima ,  Eiki Imaizumi ,  Tatsuji Matsuura

IPC: H04N005/335

CPC classification number: H04N5/357 ,  H04N5/335 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/378

Abstract: An AD-converted digital video data is encoded by a difference encoding method before it is outputted and such encoded digital video data is then outputted, after it is converted to gray code or to a predetermined code in which a fixed value is added. Problems solved include noise that is generated when the AD conversion circuit outputs video data and that migrates into a CCD side via a power supply line on a printed circuit board, and noise that appears on a display image by migration into an input terminal side from an output circuit side via the power supply line and a semiconductor substrate within an AD conversion LSI.

公开(公告)号：US20040166656A1

公开(公告)日：2004-08-26

申请号：US10785103

申请日：2004-02-25

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC: H01L021/336 ,  H01L031/062 ,  H01L031/113 ,  H01L021/3205 ,  H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US20040080293A1

公开(公告)日：2004-04-29

申请号：US10684380

申请日：2003-10-15

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Minoru Kurosawa ,  Kunihiro Kawauchi ,  Yasuhiko Kokami

IPC: H02P001/18 ,  H02P005/06

CPC classification number: H02P6/20 ,  H02M7/5395 ,  H02M2001/0009 ,  H02P6/182

Abstract: In start-up control of a motor in which currents are caused to flow through any two of three phase coils to detect the polarity of a voltage induced in each de-energized phase, thereby determining the corresponding energized phase at start-up thereof, based on the polarity of the detected induced voltage, the levels of induced voltages are detected in addition to the polarity of the induced voltage for the de-energized phase to thereby determine the relationship between the magnitudes thereof, and the energized phase at the start-up is determined based on the relationship of magnitude between the polarity of each induced voltage and the level thereof. In drive control of a multi-phase DC motor wherein a driver for allowing a drive current to flow through each coil is controlled by PWM control signals, and a sine wave-shaped current is caused to flow through each coil to thereby rotatably drive the motor, positive-phase and negative-phase signals are generated as triangular wave carrier signals for generating the PWM control signals, and the PWM control signal related to the corresponding phase coil of the respective phase coils, to which a voltage of an intermediate level is applied by the driver, is generated using a carrier signal opposite in phase to a triangular wave signal used to generate the PWM control signals for other phase coils.

Abstract translation: 在电动机的启动控制中，使电流流过三相线圈中的任意两个电流，以检测在每个去激励相位中感应出的电压的极性，从而基于在其启动时确定相应的通电阶段 对于检测到的感应电压的极性，除了去激励相的感应电压的极性之外还检测感应电压的电平，从而确定其大小与启动时的通电阶段之间的关系 基于每个感应电压的极性与其电平之间的大小关系确定。 在通过PWM控制信号控制用于允许驱动电流流过每个线圈的驱动器的多相直流电动机的驱动控制中，并且使正弦波形电流流过每个线圈从而可旋转地驱动电动机 产生正相和负相位信号作为用于产生PWM控制信号的三角波载波信号，以及与施加了中间电平的电压的各相线圈相应的相位线圈有关的PWM控制信号 由驱动器使用与用于产生其他相位线圈的PWM控制信号的三角波信号相位相反的载波信号来产生。