Abstract:
A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different fro m the first electrically conduct ive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.
Abstract:
An apparatus and a method for operating the same. The method includes providing an apparatus which includes a chamber, (200) wherein the chamber includes first (260b) and second (260a) inlets, an anode (210) and a cathode (230) structures in the chamber, and a wafer (100) on the cathode structure (230). A cleaning gas (260b) is injected into the chamber via the first inlet. A collecting gas (260a) is injected into the chamber via the second inlet. The cleaning gas when ionized has a property of etching a top surface of the wafer resulting in a by-product mixture in the chamber. The collecting gas has a property of preventing the by product mixture from depositing back to the surface of the wafer.
Abstract:
A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).
Abstract:
A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).
Abstract:
An image sensor (20) and method of fabrication wherein the sensor includes Copper (Cu) metallization levels (135a, 135b) allowing for incorporation of a thinner interlevel dielectric stack (130a-130c) to result in a pixel array (100) exhibiting increased light sensitivity. The image sensor includes structures having a minimum thickness of barrier layer metal (132a, 132b) that traverses the optical path of each pixel in the sensor array or, that have portions (50) of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer (142) may be formed atop the Cu metallization by a self-aligned deposition.
Abstract:
Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.
Abstract:
A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60b) includes forming a first sacrificial cavity layer (18) over a wiring layer (14) and substrate (10). The method further includes forming an insulator layer (40) over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity (60b) of the MEMS.
Abstract:
A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires (14) from the lower wiring layer. The method further includes forming an electrode beam (38) over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition (50).
Abstract:
A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a lower wiring layer on a substrate. The method further includes forming a plurality of discrete wires (14) from the lower wiring layer. The method further includes forming an electrode beam (38) over the plurality of discrete wires. The at least one of the forming of the electrode beam and the plurality of discrete wires are formed with a layout which minimizes hillocks and triple points in subsequent silicon deposition (50).
Abstract:
A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity (60b) includes forming a first sacrificial cavity layer (18) over a wiring layer (14) and substrate (10). The method further includes forming an insulator layer (40) over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity (60b) of the MEMS.