公开(公告)号：EP1469591A1

公开(公告)日：2004-10-20

申请号：EP04447099.5

申请日：2004-04-19

Applicant: STMicroelectronics Belgium N.V.

Inventor： Borremans, Marc

IPC: H03D7/14 ,  H03C1/54

CPC classification number: H03D7/1441 ,  H03C1/547 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/1483 ,  H03D7/1491 ,  H03D2200/0043 ,  H03D2200/0084

Abstract: An up conversion mixer has a Gilbert cell arrangement including an input amplification part (BB) for producing an amplified signal coupled to a multiplication part (RF), the multiplication part being arranged to multiply the amplified signal by a local oscillator signal (LO) and output a mixed signal, the mixer also having a capacitor (90,100,15) coupled from a node between the input amplification part and the multiplication part, to a power supply line, for suppressing unwanted high frequency signal components of the output signal of the multiplication part The linearity of such mixers can be improved considerably by this impedance on the source node of the switch transistors. This capacitance can be placed to either VSS or to VDD Notably this improvement can be achieved with low power consumption since no additional power is needed for the increased performance.

Abstract translation: 升压转换混频器具有吉尔伯特单元布置，其包括用于产生耦合到乘法部分（RF）的放大信号的输入放大部分（BB），乘法部分被布置成将放大的信号乘以本地振荡器信号（LO）和 输出混合信号，所述混频器还具有从输入放大部分和乘法部分之间的节点耦合的电容器（90,100,15）到电源线，用于抑制乘法的输出信号的不需要的高频信号分量 部分这种混频器的线性度可以通过开关晶体管的源极节点上的这种阻抗而大大提高。 该电容可以放置在VSS或VDD中。显然，这种改进可以通过低功耗实现，因为不需要额外的功率来提高性能。

公开(公告)号：EP1434142A1

公开(公告)日：2004-06-30

申请号：EP02447274.8

申请日：2002-12-24

Applicant: STMicroelectronics Belgium N.V.

Inventor： Pisoni, Fabio

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F17/141 ,  H03H2017/0214

Abstract: An M-point Fractional Fourier is described using several 2M-points traditional Fourier transforms. The signal path is fed through a series of blocks including a first multiplier, a zero pad, an FFT 2m, a second multiplier, an IFFT 2M, a 1 st half element, and a third multiplier. The first and third multipliers have as their other inputs a value exp(-j n 2 ) for n=0:M-1, derived from the clock offset signal represented by.

Abstract translation: 使用几个2M点传统傅立叶变换来描述M点分数傅里叶。 信号路径通过包括第一乘法器，零焊盘，FFT2m，第二乘法器，IFFT 2M，第一半元件和第三乘法器的一系列块馈送。 对于n = 0：M-1，第一和第三乘法器具有作为其另一个输入的值exp（-j n 2），从由...表示的时钟偏移信号导出。

公开(公告)号：EP1753193B1

公开(公告)日：2009-12-09

申请号：EP05447182.6

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro ,  Terryn, Steven ,  Schmit, Jean-Jacques

IPC: H04L27/233

CPC classification number: H04L27/22 ,  H04L7/0041 ,  H04L7/0062 ,  H04L7/007

公开(公告)号：EP2071886A1

公开(公告)日：2009-06-17

申请号：EP08165954.2

申请日：2008-10-06

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph ,  Aerts, Wouter ,  Ryder, Martin ,  Belokonskiy, Viktor

IPC: H04W16/14 ,  H04W88/06

CPC classification number: H04W48/18 ,  H04W88/06

Abstract: A first wireless transceiver apparatus for operating in a part of the RF spectrum which is shared with a co-located second wireless transceiver apparatus, the first wireless transceiver apparatus comprising:
a wireless transceiver unit;
an arbitration interface for interfacing with an arbitration entity which arbitrates access to the shared part of the RF spectrum between the first wireless transceiver apparatus and the second wireless transceiver apparatus;
wherein the arbitration interface is adapted to signal time periods when the wireless transceiver unit is operationaI or requests to be operational;
and wherein the arbitration interface is adapted to signal data about the first wireless transceiver apparatus during other time periods.

Abstract translation: 一种第一无线收发器装置，用于在与共同位置的第二无线收发器装置共享的RF频谱的一部分中操作，所述第一无线收发器装置包括：无线收发器单元; 仲裁接口，用于与仲裁实体进行接口，所述仲裁实体仲裁对所述第一无线收发器设备和所述第二无线收发器设备之间的RF频谱的共享部分的访问; 其中所述仲裁接口适于在所述无线收发器单元操作或请求可操作时发出信号时间段; 并且其中所述仲裁接口适于在其他时间段期间发送关于所述第一无线收发器装置的数据。

公开(公告)号：EP2066085A1

公开(公告)日：2009-06-03

申请号：EP07076030.1

申请日：2007-11-29

Applicant: STMicroelectronics Belgium N.V.

Inventor： Jacops, Davy ,  Van Parijs, Jorgen

IPC: H04L12/56

CPC classification number: H04L47/6215 ,  H04L47/14 ,  H04L47/50 ,  H04W72/1242 ,  H04W72/1263

Abstract: A baseband processor (20) for a Bluetooth device (80) processes packets according to a protocol stack, and uses a Bluetooth host controller interface (30) to receive packets having given priorities, from a higher protocol level or levels. Packet buffers (B1-Bn) are used to buffer the received packets, and the processor reorders the buffered packets according to their priorities, to output a prioritized stream of packets suitable for transmission by a radio part. By prioritising after the HCI interface, rather than before it, the QOS queues can be effectively located at a lower level in the stack. This means the decision made about the order of transmission of the packets, can take place later, meaning a higher probability that a high priority packet can "pass" queues of lower priority packets, and reach the air interface sooner. The reordering can involve a multiplexer (200) arranged to multiplex packets from multiplee packet buffers according to their priorities.

Abstract translation: 用于蓝牙设备（80）的基带处理器（20）根据协议栈处理分组，并且使用蓝牙主机控制器接口（30）从较高的协议级别或级别接收具有给定优先级的分组。 分组缓冲器（B1-Bn）用于缓冲接收到的分组，并且处理器根据其优先级重新排序缓冲的分组，以输出适合于由无线电部分传输的分组的优先级流。 通过在HCI接口之后的优先次序，而不是在之前，QOS队列可以有效地位于堆栈中的较低级别。 这意味着关于分组传输顺序的决定可以在稍后进行，这意味着高优先级分组可以“较低优先级分组的队列”的可能性更高，并且更快到达空中接口。 重新排序可以涉及多路复用器（200），其被布置为根据它们的优先级复用来自多个分组缓冲器的分组。

公开(公告)号：EP1434352B1

公开(公告)日：2008-08-27

申请号：EP02447268.0

申请日：2002-12-23

Applicant: STMicroelectronics Belgium N.V.

Inventor： Craninckx, Jan Frans Lucien

IPC: H03L7/18 ,  H03L7/081 ,  H03L7/089

CPC classification number: H03L7/081 ,  H03L7/0893 ,  H03L7/1976

公开(公告)号：EP1876782A1

公开(公告)日：2008-01-09

申请号：EP06013716.3

申请日：2006-07-03

Applicant: STMicroelectronics Belgium N.V.

Inventor： Wernaers, Yves

IPC: H04L27/26

CPC classification number: H04L27/2614

Abstract: A multicarrier transmission system uses a set of carriers spaced apart in frequency with a number of bits being assigned to each carrier. A transmitter (3) has a mapper (14) which maps a data signal to a parallel set of constellation values. A frequency domain-to-time domain transform stage (18) converts the set of modulated carriers to a time-domain signal. A peak detector detects when the time-domain signal exceeds a predetermined criterion. A constellation modifier (27) modifies the constellation value of at least one of the carriers to reduce the crest factor of the transmitted signal. A carrier is selected for modifying on the basis of a number of bits allocated to that carrier. The constellation modifier (27) can select an alternative constellation value by an iterative method or by calculation. The constellation modifier (27) can operate entirely in the time-domain.

Abstract translation: 多载波传输系统使用频率间隔开的一组载波，其中多个比特被分配给每个载波。 发射机（3）具有映射器（14），其将数据信号映射为并行星座值集。 频域到时域变换级（18）将该组调制载波转换为时域信号。 峰值检测器检测时域信号何时超过预定标准。 星座修改器（27）修改至少一个载波的星座值以减小发送信号的波峰因数。 根据分配给该载波的多个比特选择一个载波进行修改。 星座修改器（27）可以通过迭代方法或通过计算来选择替代星座值。 星座修改器（27）可以完全在时域中操作。

公开(公告)号：EP1753134A1

公开(公告)日：2007-02-14

申请号：EP05447184.2

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H03H17/06

CPC classification number: H03H17/0621 ,  H03H17/0685

Abstract: A receiver path comprises a means for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC (12). An interpolating filter (13) is used to generate from the first digitized samples second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit (14) is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable sample. The advantage of this arrangement is that a separate oscillator at the second sampling rate is not required while still allowing the second sampling rate to be a whole multiple of 1MHz.

Abstract translation: 一种接收机路径包括用于以第一采样速率产生从接收到的模拟信号的第一数字化样本，E.G. 到ADC（12）。 率在插滤波器（13）用于从所述第一数字化样本生成第二数字化样本哪些样品可获得的估计通过以第二采样率比所述第一采样下，第二数字化取样被输出以第一取样接收的模拟信号 采样率和包括至少一个不可用的样品。 一种电路（14）被设置用于产生一个信号，用于控制内插过滤器下游的接收路径的部件，以防止样品的不可用的处理。 这种布置的优点是没有在所述第二采样率一个独立的振荡器，而静静地允许所述第二采样率是1兆赫的整数倍不是必需的。

公开(公告)号：EP1753133A1

公开(公告)日：2007-02-14

申请号：EP05447183.4

申请日：2005-08-12

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro

IPC: H03H17/06

CPC classification number: H03H17/0621 ,  H03H17/0685

Abstract: A receive path in a receiver comprises means for deriving a first stream of first digitized samples from a received analog signal at a first sampling rate (12), and at least one interpolating filter (32,34,36) in parallel with the first stream of first digitized samples for generating at least a second stream of digitized samples at the first sampling rate but offset with respect to the first stream by a fraction of a sample time period from the first stream. This provides the advantage that a higher sample granularity can be obtained without increasing the sample rate.

Abstract translation: 接收机中的接收路径包括用于以第一采样率（12）从接收到的模拟信号导出第一数字化样本的第一流的装置，以及与第一流并行的至少一个内插滤波器（32,34,36） 第一数字化样本，用于以第一采样率产生至少第二数字化样本流，但是相对于第一流偏移来自第一流的采样时间段的一小部分。 这提供了在不增加采样率的情况下可以获得更高的样品粒度的优点。

公开(公告)号：EP1638282A1

公开(公告)日：2006-03-22

申请号：EP04077552.0

申请日：2004-09-15

Applicant: STMicroelectronics Belgium N.V.

Inventor： Latte, Olivier Rene Nicolas

IPC: H04L27/00 ,  H04B1/58

CPC classification number: H04L27/0002 ,  H03F3/45475 ,  H03F2200/541 ,  H04B1/581 ,  H04L27/2601

Abstract: A line driver circuit (250) couples a data transceiver (210,220) to a line (230). The line driver (250) comprises a differential amplifier (OA1,OA2) which receives a signal for transmission on the line. First and second feedback paths (Z1) connect between outputs of the amplifier and inputs of the amplifier. A bridge (260) couples the differential amplifier (OA1,OA2) to the line (230). The bridge comprises two matching impedance and two secondary transformer winding. Each matching impedance is connected in series with a secondary transformer winding between the outputs of the amplifiers. Two feedback branches connect between tap-points part-way along the secondary windings (262 and 261) and the inputs of the differential amplifier. The line driver circuit (250) shows low sensitivity to accuracy of component values while providing an increased dynamic on the line for a given dynamic of the transceiver and a given attenuation of the received signal.

Abstract translation: 线路驱动器电路（250）将数据收发器（210,220）耦合到线路（230）。 线路驱动器（250）包括差分放大器（OA1，OA2），其接收用于在线路上传输的信号。 第一和第二反馈路径（Z1）连接放大器的输出和放大器的输入。 桥（260）将差分放大器（OA1，OA2）耦合到线路（230）。 该桥包括两个匹配阻抗和两个次级变压器绕组。 每个匹配阻抗与放大器输出端之间的次级变压器绕组串联。 两个反馈支路沿着次级绕组（262和261）和差分放大器的输入端分接点之间连接。 线路驱动器电路（250）对分量值的精度显示低灵敏度，同时在给定的收发器动态线路上提供增加的动态以及接收信号的给定衰减。