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公开(公告)号：US11879909B2
公开(公告)日：2024-01-23
申请号：US17869301
申请日：2022-07-20
Inventor： Klodjan Bidaj , Benjamin Ardaillon , Lauriane Gateka
IPC: G01R31/00 , G01R31/26 , G01R31/28 , G01R1/02 , G01R1/04 , G01R1/067 , G01R1/073 , G01R1/18 , G01R1/24 , G01R1/28
CPC classification number: G01R1/0416 , G01R31/2808 , G01R31/2889
Abstract: A testing device for electronic dies includes a first support part and a second support part configured to be removably assembled with each other. The first and second support parts together define at least one housing where at least one electronic die can be arranged to be tested. The electronic die has a first surface with contacting elements. The at least one housing includes a first portion. This at least one housing is arranged to enable the at least one electronic die to occupy a first position in the housing where the first surface is spaced apart from the first portion, and is further arrange to enable the at least one electronic die to occupy a second position in the housing where the first surface bears against the first portion.
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公开(公告)号：US11853241B2
公开(公告)日：2023-12-26
申请号：US18065475
申请日：2022-12-13
Inventor： Jawad Benhammadi , Sylvain Meyer
IPC: G06F13/24 , G06F13/16 , G06F21/85 , H03K19/20 , G06F1/3237
CPC classification number: G06F13/24 , G06F1/3237 , G06F13/1689 , G06F21/85 , H03K19/20
Abstract: In accordance with an embodiment, an electronic device includes: an interrupt controller having an input for receiving a controller clock signal, and an output, the interrupt controller configured to deliver an output interrupt signal on the output when the controller clock signal is active, and a control circuit comprising, an input interface for receiving at least one interrupt signal likely to emanate from at least one item of equipment external to the device, a clock input for receiving an external clock signal, and a first controller connected to the input interface and to the clock input, the first controller configured to automatically generate the controller clock signal from the external clock signal from when the at least one interrupt signal is asserted until a delivery of a corresponding output interrupt signal.
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公开(公告)号：US20230384953A1
公开(公告)日：2023-11-30
申请号：US18318416
申请日：2023-05-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Jawad Benhammadi
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0604 , G06F3/0655 , G06F3/0679
Abstract: In an embodiment a method includes modifying or suppressing one or more data values of a non-volatile memory, wherein the one or more data values are stored in a first sector of the non-volatile memory, wherein the first sector is designated as a current sector by one or more selection values stored in the non-volatile memory, wherein modifying or suppressing comprises writing the one or more data values into a second sector of the non-volatile memory, and wherein the second sector is designated as an alternate sector by the one or more selection values.
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公开(公告)号：US11823750B2
公开(公告)日：2023-11-21
申请号：US17244450
申请日：2021-04-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics S.r.l.
Inventor： Philippe Sirito-Olivier , Giovanni Luca Torrisi
CPC classification number: G11C16/3454 , G11C16/105 , G11C16/26 , G11C16/30 , G11C17/00
Abstract: A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.
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公开(公告)号：US20230336176A1
公开(公告)日：2023-10-19
申请号：US18296325
申请日：2023-04-05
Applicant: STMICROELECTRONICS S.r.l. , STMICROELECTRONICS (ALPS) SAS
Inventor： Antonino CONTE , Marco RUTA , Michelangelo PISASALE , Thomas JOUANNEAU
IPC: H03K19/0185 , H03K19/20
CPC classification number: H03K19/018521 , H03K19/20
Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.
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Patent Agency Ranking
公开(公告)号：US20230327666A1
公开(公告)日：2023-10-12
申请号：US18191491
申请日：2023-03-28
Inventor： Matthieu Desvergne , Marc Sabut , Emmanuel Allier , Thierry Masson
IPC: H03K17/687 , H03K17/22 , H03K17/10
CPC classification number: H03K17/6871 , H03K17/223 , H03K17/102
Abstract: In an embodiment a switch includes a first MOS transistor having its source connected to its channel-forming region and coupled with a first terminal of the switch, its drain coupled with a second terminal of the switch, and its gate connected to a first node of the switch, a diode coupling the first terminal with the first node, a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch and a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold.
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公开(公告)号：US11764731B2
公开(公告)日：2023-09-19
申请号：US18059812
申请日：2022-11-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS , STMicroelectronics S.r.l.
CPC classification number: H03B5/36 , G06F1/10 , H03F3/245 , H04B1/0475 , H03B2200/004 , H03F2200/451 , H04B2001/0408
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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公开(公告)号：US11754684B2
公开(公告)日：2023-09-12
申请号：US16888334
申请日：2020-05-29
Applicant: STMicroelectronics (Alps) SAS
Inventor： Romain David , Xavier Branca
CPC classification number: G01S7/484 , G01S17/10 , H01S5/0428 , H01S5/062
Abstract: The present disclosure relates to a driver circuit for an optical light emitter of a ranging device, the driver circuit comprising: an inductor having a first of its nodes coupled to a current driver; a first branch comprising a first switch coupled between the second node of the inductor and a first supply voltage rail; a second branch for conducting a current through the optical light emitter, the second branch being coupled between the second node of the inductor and the first supply voltage rail; and a current sensor configured to detect the current passing through the inductor and to provide a feedback signal to the current driver.
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公开(公告)号：US11742757B2
公开(公告)日：2023-08-29
申请号：US17650463
申请日：2022-02-09
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
CPC classification number: H02M3/158 , H02M1/36 , H02M1/0045
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US11710976B2
公开(公告)日：2023-07-25
申请号：US17187478
申请日：2021-02-26
Inventor： Alexandre Pons , Jean Camiolo , Meriem Mersel
CPC classification number: H02J7/00712 , H02J7/007192 , H02J2207/20 , H02J2207/30
Abstract: An embodiment of the present disclosure relates to a power supply interface comprising: a converter delivering a first DC voltage; a resistor connected between the converter and an output terminal of the interface delivering a second DC voltage; a first circuit delivering a second signal representative of a difference between the second DC voltage and a voltage threshold when a first signal is in a first state, and at a default value otherwise; a second circuit delivering a third signal representative of a value of a current in first resistor multiplied by a gain of the third circuit, and modifying the gain based on the second signal; and a third circuit configured to deliver a signal for controlling the converter based at least on the third signal.
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