公开(公告)号：WO1996035145A1

公开(公告)日：1996-11-07

申请号：PCT/US1996005224

申请日：1996-04-17

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  WAMPLER, Kurt, E. ,  LAIDIG, Thomas, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G03F07/20

CPC classification number: G03F7/70441 ,  G03F1/36 ,  H01J2237/31762 ,  H01J2237/31769

Abstract: A method for synthesizing correction features for an entire mask pattern that initially divides mask pattern data into tiles of data - each tile representing an overlapping section of the original mask pattern. Each of the tiles of data is sequentially processed through correction feature synthesis phases - each phase synthesizing a different type of correction feature. All of the correction features are synthesized for a given tile before synthesizing the correction features for the next tile. Each correction feature synthesis phase formats the data stored in the tile into a representation that provides information needed to synthesize the correction feature for the given phase. Methods for implementing edge bar and serif correction features synthesis phases are also described. The method for synthesizing external type edge bars is performed by oversizing feature data in the tile by an amount equal to the desired spacing of the external edge bar, formatting the oversized data into an edge representation and expanding each of the edges in the edge representation of the oversized data into edge bars having a predetermined width. Internal type of edge bars for the tile are synthesized by initially inverting feature data and then performing the same steps as for generating the external edge bars. The method for serif synthesis is performed by initially formatting tile data into a vertex representation, eliminating certain of the vertices not requiring serifs, synthesizing a positive serif for each convex corner and a negative vertex for each concave corner, and eliminating any disallowed serifs. Internal bars and negative serifs are "cut-out" of original tile data by performing geometric Boolean operations and external bars and positive serifs are concatenated with the "cut-out" tile data, equivalent to performing a geometric OR operation.

Abstract translation: 一种用于将最初将掩模图案数据划分成数据块的整个掩模图案的校正特征的方法，每个图块表示原始掩模图案的重叠部分。 通过校正特征合成阶段顺序地处理每个数据块，每个相合成不同类型的校正特征。 在为下一个瓦片合成修正特征之前，对于给定的瓦片合成所有校正特征。 每个校正特征合成阶段将存储在瓦片中的数据格式化为提供合成给定阶段的校正特征所需的信息的表示。 还描述了实现边缘条和衬里修正特征合成阶段的方法。 用于合成外部边缘条的方法是通过将瓦片中的特征数据超过等于外部边缘条的期望间隔的量来执行的，将大尺寸数据格式化为边缘表示，并且将边缘表示中的每个边缘扩展 超大数据进入具有预定宽度的边条。 通过初始反转特征数据然后执行与产生外边缘条相同的步骤来合成瓦片的边缘条的内部类型。 用于衬线合成的方法是通过将瓦片数据初始格式化为顶点表示，消除某些不需要衬线的顶点，为每个凸角合成一个正衬线和每个凹角的负顶点，以及消除任何不允许的衬线。 内部柱和负衬里是通过执行几何布尔运算和外部柱而将原始瓦片数据“切出”，正衬线与“切出”瓦片数据连接，相当于执行几何或运算。

公开(公告)号：WO1996023364A1

公开(公告)日：1996-08-01

申请号：PCT/US1995012566

申请日：1995-10-12

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  CORRY, Alan, G. ,  PURI, Manoj ,  SUTHERLAND, Robert, A.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: H04B01/10

CPC classification number: G06K9/0057 ,  G06K9/0051

Abstract: An apparatus and method for decorrelating pairs of mutually contaminated channels in a multi-channel digital signal including two identical data processing paths and a feedback path. Each pair of mutually contaminated channels consists of a first contamined channel and a second contaminated channel. Initially, first and second shifted signals are generated by shifting the original contaminated signal such that the first shifted signal has the first contaminated channel centered at zero frequency and the second shifted signal has the second contaminated channel centered at zero frequency. Each of the first and second shifted signals are coupled to one of the two identical signal processing paths. The first path generates an error corruption component corresponding to the first shifted input signal and subtracts this corruption component from the second shifted signal in order to generate a third decorrelated digital signal. The second path generates an error corruption component corresponding to the second shifted input signal and subtracts it from the first shifted signal in order to generate a fourth decorrelated digital signal. The feedback path generates a current average error correlation factor by multiplying the third and fourth to generate an instantaneous error factor and summing this with the previous average error correlation factor for all samples. The current average error correlation factor is used to generate the first and second error corruption components. Each of the corrupted channels in the original contamined digital signal are decorrelated when the third and fourth digital signals are decorrelated.

Abstract translation: 一种用于在包括两个相同的数据处理路径和反馈路径的多通道数字信号中去相互关联相互污染的通道的装置和方法。 每对相互污染的通道由第一被检测通道和第二污染通道组成。 首先，通过移动原始污染信号来产生第一和第二移位信号，使得第一移位信号具有以零频率为中心的第一污染信道，并且第二移位信号具有以零频率为中心的第二污染信道。 第一和第二移位信号中的每一个耦合到两个相同的信号处理路径之一。 第一路径产生与第一移位输入信号对应的错误损坏部件，并从第二移位信号中减去该损坏部件，以产生第三解相关数字信号。 第二路径产生与第二移位输入信号对应的错误损坏部件，并将其从第一移位信号中减去，以产生第四解相关数字信号。 反馈路径通过乘以第三和第四来产生当前平均误差相关因子以产生瞬时误差因子，并将其与所有样本的先前平均误差相关因子相加。 当前的平均误差相关因子用于产生第一和第二错误损坏组件。 当第三和第四数字信号被去相关时，原始被检查的数字信号中的每个被破坏的信道都被去相关。

公开(公告)号：WO1996003750A1

公开(公告)日：1996-02-08

申请号：PCT/US1995009366

申请日：1995-07-25

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC. ,  BATEMAN, Bruce, L.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC.

IPC: G11C05/14

CPC classification number: G11C5/143 ,  G11C7/062

Abstract: A circuit for protecting an interconnect line from certain undesirable voltage swings for a given input signal. A transmission gate is coupled in series between the input signal and the interconnect line. The transmission gate's input terminal is coupled to the input signal, its output terminal is coupled to the interconnect line, and its control terminal is coupled to the output of an inverter. The input of the inverter is coupled to the input signal. When the input signal transitions to a voltage that exceeds the trip point of the inverter, the inverter outputs a signal that disables the transmission gate such that the node is isolated from the input signal. A PFET transmission gate is utilized for protection against voltages that are too negative, and an NFET transmission gate is utilized for protection against voltages that are too positive. The inverter may be replaced by a comparator having its positive input coupled to a reference voltage and its negative input coupled to the input signal. The reference voltage determines the trip point of the protection circuit. The protection circuit may also include first and second biased MOS devices (having different channel types) coupled between first and second working potentials. The gate of the first MOS device is coupled to the input signal and the gate of the second MOS device is coupled to the output of the inverter. The MOS devices function as a conductive voltage divider network to establish a voltage on the node when the node is isolated from the input signal.

Abstract translation: 用于保护互连线免于给定输入信号的某些不期望的电压摆动的电路。 传输门串联在输入信号和互连线之间。 传输门的输入端耦合到输入信号，其输出端耦合到互连线，其控制端耦合到逆变器的输出。 反相器的输入耦合到输入信号。 当输入信号转换到超过变频器跳闸点的电压时，变频器输出禁止传输门的信号，使得节点与输入信号隔离。 PFET传输门用于防止太负电压的保护，并且NFET传输门被用于防止过大的电压。 反相器可以由比较器代替，其比较器的正输入耦合到参考电压，其负输入耦合到输入信号。 参考电压确定保护电路的跳变点。 保护电路还可以包括耦合在第一和第二工作电位之间的第一和第二偏置MOS器件（具有不同的沟道类型）。 第一MOS器件的栅极耦合到输入信号，第二MOS器件的栅极耦合到反相器的输出端。 MOS器件用作导电分压器网络，以在节点与输入信号隔离时在节点上建立电压。

公开(公告)号：WO1995005033A1

公开(公告)日：1995-02-16

申请号：PCT/US1994004613

申请日：1994-04-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/018

CPC classification number: H03K19/017563 ,  H03K19/013 ,  H03K19/01831

Abstract: An apparatus for reducing transmisson delay times when transmitting differential signals in an integrated circuit along long interconnect lines (10, 11) includes a current mode line driver which converts the differential signal to be transmitted into a signal that has a relatively low peak-to-peak voltage and large differential current changes. A receiver responsive to differential current changes converts the signal back into an output differential signal having peak-to-peak voltages adaptable to subsequent logic stages. A feedback circuit (Q5, Q6) coupled to the interconnect lines (10, 11) and the receiver functions to clamp the interconnect lines (10, 11) to a predetermined voltage while allowing the output differential signal to have peak-to-peak voltages greater than the predetermined voltage.

Abstract translation: 一种用于在沿着长互连线（10,11）的集成电路中传输差分信号时减小透射延迟时间的装置包括：电流模式线驱动器，其将待传输的差分信号转换成具有相对低的峰 - 峰值电压和大差分电流变化。 响应于差分电流变化的接收器将信号反馈回具有适应于后续逻辑级的峰 - 峰电压的输出差分信号。 耦合到互连线（10,11）的反馈电路（Q5，Q6）和接收器用于将互连线（10,11）钳位到预定电压，同时允许输出差分信号具有峰 - 峰电压 大于预定电压。

公开(公告)号：WO1994005085A1

公开(公告)日：1994-03-03

申请号：PCT/US1993005106

申请日：1993-05-28

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  WONG, Ban, Pak

IPC: H03K19/0944

CPC classification number: H03K19/018521 ,  H03K19/00361 ,  H03K19/0136 ,  H03K19/017518

Abstract: An ECL-to-CMOS level translator and BiCMOS buffer are described. The current supplied from the first input PMOS transistor (P1) is the input current to a current mirror comprising the first and second NMOS transistors (N1 and N2). The current mirror controls the current sourcing and sinking capability of the translator. Third and fourth NMOS transistors (N3 and N4) are coupled to the first and second NMOS transistors in the current mirror and function to vary the source-to-body voltage of the first and second NMOS transistors and consequently their gain which results in increased current drive and sinking capability. The BiCMOS differential buffer of the present invention provides a differential output signal on first and second output nodes (115 and 215). It is comprised of first and second cross-coupled buffers (100B and 200B). Cross-coupling the buffers results in improved high-to-low transition times.

Abstract translation: 描述了ECL到CMOS电平转换器和BiCMOS缓冲器。 从第一输入PMOS晶体管（P1）提供的电流是包括第一和第二NMOS晶体管（N1和N2）的电流镜的输入电流。 当前镜像控制翻译器的当前采样和下载功能。 第三和第四NMOS晶体管（N3和N4）耦合到电流镜中的第一和第二NMOS晶体管，并且用于改变第一和第二NMOS晶体管的源极体电压，并因此改变其增益，从而导致电流增加 驱动和下沉能力。 本发明的BiCMOS差分缓冲器在第一和第二输出节点（115和215）上提供差分输出信号。 它由第一和第二交叉耦合缓冲器（100B和200B）组成。 交叉耦合缓冲区导致改进的高到低的转换时间。

公开(公告)号：WO1993017498A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001894

申请日：1993-02-23

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  ROSSEEL, Geert ,  HERNDON, William, H. ,  MATTHEWS, James, A.

IPC: H03K17/16

CPC classification number: H03K19/086 ,  H03K17/14 ,  H03K17/567 ,  H03K17/603 ,  H03K19/09448

Abstract: An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.

Abstract translation: 改进的BiCMOS逻辑电路（70）利用发射极耦合的双极晶体管（21,22）来差分地比较输入信号（Vin）与逻辑参考电平（VBIAS）。 每个双极晶体管由并联耦合的p沟道金属氧化物半导体（PMOS）晶体管（26,27）的网络进行电阻负载。 晶体管的并联组合中的至少一个具有耦合到提供可变负载电阻的控制信号（VREF2）的栅极。 控制信号优选地由反馈网络（52,53）提供，反馈网络（52,53）通过温度在网络上保持恒定的电压摆幅。

公开(公告)号：WO1992017745A1

公开(公告)日：1992-10-15

申请号：PCT/US1992002622

申请日：1992-03-31

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: F28F07/02

CPC classification number: F28F3/12 ,  F28D2021/0029 ,  F28F2260/02 ,  H01L23/473 ,  H01L2924/0002 ,  Y10T29/49366 ,  Y10T29/49368 ,  H01L2924/00

Abstract: A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates (10), laminated together to form a block (18). Each plate has a pair of holes (14, 15) cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

公开(公告)号：WO1991011019A1

公开(公告)日：1991-07-25

申请号：PCT/US1991000211

申请日：1991-01-10

Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.

Inventor： MICROUNITY SYSTEMS ENGINEERING, INC. ,  MATTHEWS, James, A.

IPC: H01L21/225

CPC classification number: H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136 ,  H01L2924/00

Abstract: A method for forming a BICMOS integrated circuit having MOS field effect transistors and bipolar junction transistors is disclosed. The process comprises first defining separate active areas, forming a gate dielectric layer and a first layer of polysilicon. This polysilicon is then selectively etched to form a plurality of equally-spaced first polysilicon members comprising the gates (33, 34) of the MOS transistors and the extrinsic base contacts (35) of the NPN transistors. After insulating the first polysilicon members, an additional layer of polysilicon is deposited over the substrate to replanarize the entire wafer surface. The additional layer of polysilicon is then etched to form a plurality of second polysilicon members (65, 66, 67, 68, 69). Impurities are diffused from the polysilicon members to form source/drain regions (73, 74, 75, 76) of the MOS transistors and the extrinsic base (81) and emitter (77) regions of the NPN transistors. The final processing steps include providing the interconnection of the MOS and NPN transistors.

公开(公告)号：WO2004039131A2

公开(公告)日：2004-05-06

申请号：PCT/US2003/033747

申请日：2003-10-24

Applicant: COMPLEX SYSTEMS ENGINEERING, INC. ,  JACEK, Marczyk

Inventor： JACEK, Marczyk

IPC: H05F

CPC classification number: G06N7/02 ,  G06F17/5009 ,  G06F2217/10

Abstract: A process for the computer creation of fuzzy cognitive maps (see Fig. 7) that are used to explore causal relationships between a group of factors and a phenomenon. These fuzzy cognitive maps are constructed using the data derived from Expanded Meta Models. These Expanded Meta Models are generated from Monte Carlo simulations that supply the factors under investigation with values, then by incrementing or decrementing these factor values one can generated an Expanded Meta Model.

Abstract translation: 计算机创建模糊认知图（见图7）的过程，用于探索一组因素与现象之间的因果关系（302）。 这些模糊认知图是使用从扩展元模型得到的数据构建的（25）。 这些扩展元模型是从蒙特卡罗模拟中产生的，这些模拟通过数值提供被调查的因素，然后通过递增或递减这些因子值，可以生成扩展元模型（25）。

公开(公告)号：WO2004026687A2

公开(公告)日：2004-04-01

申请号：PCT/US2003/025726

申请日：2003-08-18

Applicant: AERO SYSTEMS ENGINEERING INC. ,  HATLESTAD, Kathryn, W. ,  LINDAHL, Bruce, C. ,  MOSES, Kent, J.

Inventor： HATLESTAD, Kathryn, W. ,  LINDAHL, Bruce, C. ,  MOSES, Kent, J.

IPC: B64D

CPC classification number: B64D23/00

Abstract: A free fall simulator with a flight chamber, a fan system to generate airflow in the flight chamber, and a noise attenuation housing substantially enclosing the fan system.

Abstract translation: 具有飞行室的自由落体模拟器，在飞行室中产生气流的风扇系统，以及基本上包围风扇系统的噪声衰减壳体。