公开(公告)号：WO2010027715A1

公开(公告)日：2010-03-11

申请号：PCT/US2009/054707

申请日：2009-08-22

Applicant: TOKYO ELECTRON LIMITED ,  HASEGAWA, Toshio ,  LEUSINK, Gerrit, J. ,  TOKYO ELECTRON AMERICA, INC.

Inventor： HASEGAWA, Toshio ,  LEUSINK, Gerrit, J.

IPC: H01L21/337 ,  H01L29/808

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/517

Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonithde gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonithde film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonithde film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.

Abstract translation: 描述了一种用于形成用于半导体器件的掺铝金属（钽或钛）碳化硅栅极电极的方法。 该方法包括在其上提供含有电介质层的衬底，以及在不存在等离子体的情况下在电介质层上形成栅电极。 栅电极通过沉积金属碳化硅膜并在金属碳化硅膜上吸附铝前体的原子层而形成。 沉积和吸附的步骤可以重复所需的次数，直到掺杂铝的金属碳氮化物栅极具有期望的厚度。

公开(公告)号：WO2005096352A3

公开(公告)日：2009-02-26

申请号：PCT/US2005000916

申请日：2005-01-12

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  ROY PRADIP K ,  DIP ANTHONY ,  LEITH ALLEN J ,  OH SEUNGHO

Inventor： ROY PRADIP K ,  DIP ANTHONY ,  LEITH ALLEN J ,  OH SEUNGHO

IPC: H01L21/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L21/67109 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2807 ,  H01L29/161

Abstract: A SiGe thin layer semiconductor structure containing a substrate (400, 500, 600) having a dielectric layer (410, 510, 610), a variable composition SixGe1-x layer (440, 520, 620) on dielectric layer (410, 510, 610), and a Si cap layer (450, 530, 630) on the variable composition SixGe1x layer (440, 520, 620). The variable composition SixGe1-x layer (440, 520, 620) can contain a SixGe1-x layer (520, 620) with a graded Ge content or a plurality of SixGe1-x. sub-layers (420, 430) each with different Ge content (421, 431). In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate (600) having a dielectric layer (610), a Si­-containing seed layer (615) on the dielectric layer (610), a variable composition SixGe1-x layer (620) on the seed layer (615), and a Si cap layer (630) on the variable composition SixGe 1-x layer (620). A method and processing tool (1, 100) for fabricating the SiGe thin layer semiconductor structure are also provided.

Abstract translation: 一种SiGe薄层半导体结构，其包含在电介质层（410,510,620）上具有介电层（410,510,610），可变组成物SixGe1-x层（440,520,620）的衬底（400,500,600） 610）和可变组成SixGe1x层（440,520,620）上的Si覆盖层（450,530,630）。 可变成分SixGe1-x层（440,520,620）可以包含具有分级Ge含量或多个SixGe1-x的SixGe1-x层（520,620）。 每个具有不同Ge含量的子层（420,430）（421,431）。 在本发明的一个实施例中，SiGe薄层半导体结构包含在电介质层（610）上具有介电层（610），含Si种子层（615）的半导体衬底（600），可变组合物SixGe1- x2层（620）上，以及位于可变组成SixGe 1-x层（620）上的Si覆盖层（630）。 还提供了一种用于制造SiGe薄层半导体结构的方法和处理工具（100）。

公开(公告)号：WO2008109504A3

公开(公告)日：2008-12-18

申请号：PCT/US2008055623

申请日：2008-03-03

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  LIMURO SHUNICHI

Inventor： LIMURO SHUNICHI

IPC: H01L21/00

CPC classification number: H01L21/67173 ,  H01L21/67196 ,  H01L21/67742

Abstract: Embodiments of apparatus (100) and methods for performing high throughput non-plasma processing are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于执行高通量非等离子体处理的装置（100）和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：WO2007118042A3

公开(公告)日：2008-11-27

申请号：PCT/US2007065756

申请日：2007-04-02

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  CERIO FRANK M JR

Inventor： CERIO FRANK M JR

IPC: C23C14/34 ,  C23C14/35

CPC classification number: C23C14/046 ,  C23C14/18 ,  C23C14/354

Abstract: An iPVD system (200A) is programmed to deposit a barrier and/or seed layer (10) using a Ru-containing material into high aspect ratio nano-size features on semiconductor substrates (12, 211 ) using a process which enhances the sidewalÊ (16) coverage compared to the field and bottom (15) coverage(s) while minimizing or eliminating overhang within an IPVD processing chamber (220). In the preferred embodiment, an IPVD apparatus having a frusto-conical ruthenium target (225) equipped with a high density ICP source is provided.

Abstract translation: iPVD系统（200A）被编程为使用增强侧翼的过程，将使用含Ru材料的阻挡层和/或种子层（10）沉积到半导体衬底（12,211）上的高纵横比纳米尺寸特征中 16）与现场和底部（15）覆盖相比，同时最小化或消除IPVD处理室（220）内的突出。 在优选实施例中，提供了具有配备有高密度ICP源的截头圆锥形钌靶（225）的IPVD装置。

公开(公告)号：WO2008100846A3

公开(公告)日：2008-11-06

申请号：PCT/US2008053561

申请日：2008-02-11

Applicant: TOKYO ELECTRON LTD ,  TOKYO ELECTRON AMERICA INC ,  DIP ANTHONY

Inventor： DIP ANTHONY

IPC: C23C16/455 ,  H01L21/00

CPC classification number: C23C16/45551 ,  C23C16/45508 ,  C23C16/45519 ,  C23C16/45536 ,  C23C16/4584 ,  C23C16/54 ,  H01L21/68764 ,  H01L21/68771

Abstract: Systems and methods for depositing thin films using Atomic Layer Deposition (ALD). The deposition system (10) includes a process chamber (16) with a peripheral sidewall (36), partitions (68, 70, 72, 74) that divide a processing space (38) inside the process chamber (16) into at least two compartments (76, 78), and a platter (50) that supports substrates (15) within the processing space (38). The platter (50) rotates the substrates (15) relative to the stationary peripheral sidewail (36) and compartments (76, 78). One compartment (76) receives a process material used to deposit a layer on each of the substrates (15) and the other compartment (78) contains an inert gas. A material injector (100, 100a, 100b), which injects the process materia!, communicates with the compartment (76) through the peripheral sidewall (36).

Abstract translation: 使用原子层沉积（ALD）沉积薄膜的系统和方法。 沉积系统（10）包括具有外围侧壁（36）的处理室（16），将处理室（16）内部的处理空间（38）分成至少两个的分隔壁（68,70,72,74） 隔室（76,78）和支撑处理空间（38）内的基板（15）的盘（50）。 盘片（50）相对于固定的周边侧翼（36）和隔间（76,78）旋转衬底（15）。 一个隔室（76）接收用于在每个基板（15）上沉积层的工艺材料，另一隔室（78）包含惰性气体。 注射过程材料的注射器（100,100a，100b）通过周边侧壁（36）与隔室（76）连通。

公开(公告)号：WO2008112673A3

公开(公告)日：2008-09-18

申请号：PCT/US2008/056478

申请日：2008-03-11

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  SUNDARARAJAN, Radha ,  CHEN, Lee ,  FUNK, Merritt

Inventor： SUNDARARAJAN, Radha ,  CHEN, Lee ,  FUNK, Merritt

IPC: H01L21/687 ,  C23C16/458

Abstract: Control of radial or non-radial temperature distribution is controlled across a substrate during processing to compensate for non-uniform effects, including non-uniformities arising from system or process. Temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck (substrate support table 20, 20a) to vary heat conduction across the wafer. Ports (26, 26a) in the support table (20, 20a) are grouped, and gas to or from the groups is separately controlled by different valves (32) responsive to a controller (35) that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities. Wafer deformation is affected by separately controlling the pressure of the backside gas at different ports (26, 26a) to control the local force exerted on the backside of the substrate, by separately dynamically controlling valves (32) affecting gas flow to a port (26, 26a) and ports (26, 26a) surrounding said port (26, 26a).

公开(公告)号：WO2008095154A1

公开(公告)日：2008-08-07

申请号：PCT/US2008/052760

申请日：2008-02-01

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  HERZOG, Frank

Inventor： HERZOG, Frank

IPC: H01L21/67

CPC classification number: H01L21/67309

Abstract: A boat (50) is provided for stacking semiconductor wafers (20) vertically in processes in which low friction deposits may coat wafer supporting surfaces and allow the wafers to slip sideways in the boat, leaving them sufficiently out of alignment to cause wafer breakage in handling. Typical boats for these processes have vertical legs (52) in which aligned notches (58) support the wafers. The notches provide enough clearance around the edge of the wafers to facilitate loading and unloading of the wafers without wafer damage, as long as the wafers remain centered. With the invention, each notch has a shallow recess (66) on which the edge of a wafer can rest. The recess adds a low step close to the wafer edge that resists horizontal sliding movement of the wafer. Wafers inserted into the boat in a plane spaced above the steps, then lowered onto the recesses.

Abstract translation: 提供了用于在低摩擦沉积物可以涂覆晶片支撑表面并允许晶片在船上侧向滑动的过程中垂直地堆叠半导体晶片（20）的船（50），使得它们足够地不对准，从而导致晶片在处理中的破裂 。 用于这些工艺的典型的船只具有垂直的腿部（52），其中对齐的凹口（58）支撑晶片。 只要晶片保持居中的位置，切口在晶片的边缘周围提供足够的间隙，以便于晶片的加载和卸载，而没有晶片损坏。 利用本发明，每个凹口具有浅凹槽（66），晶片的边缘可以在其上搁置。 凹槽附近靠近晶片边缘的低台阶，抵抗晶片的水平滑动运动。 将晶片在与台阶间隔开的平面上插入船中，然后下降到凹槽上。

公开(公告)号：WO2008042691A2

公开(公告)日：2008-04-10

申请号：PCT/US2007/079667

申请日：2007-09-27

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  MATSUDA, Tsukasa ,  SAKURAGI, Isamu

Inventor： MATSUDA, Tsukasa ,  SAKURAGI, Isamu

IPC: C23C16/02 ,  C23C16/452 ,  C23C16/455 ,  C23C16/04 ,  C23C16/18 ,  C23C16/56

CPC classification number: C23C16/0236 ,  C23C16/045 ,  C23C16/18 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/56

Abstract: A processing system (1, 504B) and method for integrated substrate processing in a substrate processing tool (500). The processing system (1, 504B) contains a substrate holder (20) configured for supporting and controlling the temperature of the substrate (25), a hot filament hydrogen radical source (31 ) for generating hydrogen radicals, and a controller (70, 510) configured for controlling the processing system (1, 504B). The hot filament hydrogen radical source (31 ) includes a showerhead assembly (30) containing an internal volume (37) and a showerhead plate (35) having gas passages (33) facing the substrate (25) for exposing the substrate (25) to the hydrogen radicals, and at least one meta! wire filament (59, 59a, 59b, 59c) within the interna! volume (37) to thermaliy dissociate H2 gas into the hydrogen radicals. The integrated process includes pretreating exposed surfaces of an etch feature (105) in a dielectric film (113, 115, 624, 626) and an exposed metal interconnect pattern (111 A, 622A) formed underneath the etch feature (105) with a flow of hydrogen radicals generated by thermal decomposition of H2 gas by a hot filament hydrogen radical source (31 ) separated from the substrate (25) by a showerhead plate (35) containing gas passages (33) facing the substrate (25). The integrated process further includes depositing a barrier metal film (116, 628) over the pretreated exposed surfaces, and forming a Cu metal film (113) on the barrier metal film (116, 628).

Abstract translation: 一种用于衬底处理工具（500）中的集成衬底处理的处理系统（1,504B）和方法。 处理系统（1,504B）包括：衬底保持器（20），其构造成用于支撑和控制衬底（25）的温度，用于产生氢自由基的热丝氢自由基源（31）;以及控制器 ）配置用于控制处理系统（1,504B）。 热丝氢自由基源（31）包括含有内部体积（37）和喷头板（35）的喷头组件（30），喷头板（35）具有面向衬底（25）的气体通道（33），用于将衬底（25）暴露于 氢自由基和至少一个元素 内部的丝线（59,59a，59b，59c） 体积（37）以将H2气体热分解成氢自由基。 整合过程包括在介电膜（113,115,624,626）中预处理蚀刻特征（105）的暴露表面，以及形成在蚀刻特征（105）下方的暴露的金属互连图案（111A，622A） 由通过包含面向衬底（25）的气体通道（33）的喷头板（35）与基底（25）分离的热丝氢自由基源（31）由H2气体的热分解产生的氢自由基。 整合过程还包括在预处理的暴露表面上沉积阻挡金属膜（116,628），以及在阻挡金属膜（116,628）上形成Cu金属膜（113）。

公开(公告)号：WO2008030713A1

公开(公告)日：2008-03-13

申请号：PCT/US2007/076734

申请日：2007-08-24

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  MIZOTA, Shogo ,  TERUOMI, Minami ,  YOKOMIZO, Kenji ,  MASAKI, Taira

Inventor： MIZOTA, Shogo ,  TERUOMI, Minami ,  YOKOMIZO, Kenji ,  MASAKI, Taira

IPC: H01L21/02

CPC classification number: H01L21/02052 ,  H01L21/02057 ,  Y10S134/902

Abstract: A method is provided for reducing the amount of film fragments (66a) discharged into a processing liquid circulation system (73, 73') during removal of films (66) from wafers (W), thereby reducing the frequency of filter (80) cleaning or filter (80) replacement. The method includes exposing a wafer (W) containing a film (66) formed thereon in a process chamber (46) of a substrate processing system (1) to a processing liquid (64), where the wafer (W) is not rotated or is rotated at a first speed (608a, 908a, 1208a) and the processing liquid (64) is discharged from the process chamber (46) to a processing liquid circulation system (73). Subsequently, exposure of the wafer (W) to the processing liquid (64, 64a, 64b) is discontinued and the wafer (W) is rotated at a second speed (608b, 908b, 1208b) greater than the first speed (608a, 908a, 1208a) to centrifugally remove fragments (66a) of the film (66) from the wafer (W). Next, the wafer (W) is exposed to the same or a different processing liquid (64, 64a, 64b) and the processing liquid (64, 64a, 64b) is discharged from the process chamber (46) to a processing liquid drain (78).

Abstract translation: 提供一种用于减少在从晶片（W）移除薄膜（66）期间排出到处理液体循环系统（73,73'）中的薄膜碎片（66a）的量的方法，从而降低过滤器（80）清洁的频率 或过滤器（80）更换。 该方法包括将其上形成的膜（66）的晶片（W）暴露在基板处理系统（1）的处理室（46）中的处理液体（64）中，其中晶片（W）不旋转或 以第一速度（608a，908a，1208a）旋转，并且处理液体（64）从处理室（46）排出到处理液循环系统（73）。 随后，将晶片（W）暴露于处理液（64,64a，64b）中断，晶片（W）以比第一速度（608a，908a）大的第二速度（608b，908b，1208b）旋转 ，1208a）从晶片（W）离心去除膜（66）的碎片（66a）。 接下来，将晶片（W）暴露于相同或不同的处理液（64,64a，64b），处理液（64,64a，64b）从处理室（46）排出到处理液排出口 78）。

公开(公告)号：WO2008021654A3

公开(公告)日：2008-02-21

申请号：PCT/US2007/073972

申请日：2007-07-20

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON AMERICA, INC. ,  TAKAHASHI, Hiroyuki

Inventor： TAKAHASHI, Hiroyuki

IPC: H01J37/32 ,  C23C16/44

Abstract: An exhaust assembly is described for use in a plasma processing system (10, 100, 110, 200, 300, 500, 600, 700), whereby secondary plasma is formed in the exhaust assembly (140, 240, 334) between the processing space and chamber exhaust ports in order to reduce plasma leakage (18) to a vacuum pumping system (16, 130, 330), or improve the uniformity of the processing plasma, or both. The exhaust assembly (140, 240, 334) includes a powered exhaust plate (142, 242) in combination with a ground electrode (244) is utilized to form the secondary plasma surrounding a peripheral edge of a substrate treated in the plasma processing system.