公开(公告)号：US07293183B2

公开(公告)日：2007-11-06

申请号：US10647990

申请日：2003-08-26

Applicant: Jin-aeon Lee ,  Yun-tae Lee

Inventor： Jin-aeon Lee ,  Yun-tae Lee

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3246 ,  Y02D10/152 ,  Y02D50/20

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working context restored to the memory from the non-volatile memory.

Abstract translation: 提供了一种发送工作环境的装置和方法，其可以使包括芯片上的系统的便携式设备的断电待机模式中的功率消耗最小化，其中该方法包括选择断电待机模式， 将安装在半导体芯片上的硬件模块相对于预定存储器，并将工作上下文存储在预定存储器中，将存储在存储器中的工作上下文传送到半导体芯片外部的非易失性存储器，并存储 非易失性存储器中的工作环境，以及执行掉电待机模式; 其中所述方法还可以包括释放所述断电待机模式，将存储在所述非易失性存储器中的所述硬件模块的工作上下文恢复到所述预定存储器，以及将所述至少一个硬件模块恢复到 在通过使用从非易失性存储器恢复到存储器的工作上下文执行关闭待机模式之前存在的状态。

公开(公告)号：US20070214376A1

公开(公告)日：2007-09-13

申请号：US11747774

申请日：2007-05-11

Applicant: Jin-aeon LEE ,  Yun-tae Lee

Inventor： Jin-aeon LEE ,  Yun-tae Lee

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3246 ,  Y02D10/152 ,  Y02D50/20

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working context restored to the memory from the non-volatile memory.

Abstract translation: 提供了一种发送工作环境的装置和方法，其可以使包括芯片上的系统的便携式设备的断电待机模式中的功率消耗最小化，其中该方法包括选择断电待机模式， 将安装在半导体芯片上的硬件模块相对于预定存储器，并将工作上下文存储在预定存储器中，将存储在存储器中的工作上下文传送到半导体芯片外部的非易失性存储器，并存储 非易失性存储器中的工作环境，以及执行掉电待机模式; 其中所述方法还可以包括释放所述断电待机模式，将存储在所述非易失性存储器中的所述硬件模块的工作上下文恢复到所述预定存储器，以及将所述至少一个硬件模块恢复到 在通过使用从非易失性存储器恢复到存储器的工作上下文执行关闭待机模式之前存在的状态。

公开(公告)号：US09036051B2

公开(公告)日：2015-05-19

申请号：US13542921

申请日：2012-07-06

Applicant: Jung Chak Ahn ,  Yun Tae Lee ,  Bum Suk Kim ,  Tae Chan Kim ,  Jung Hoon Jung ,  Tae Sub Jung

Inventor： Jung Chak Ahn ,  Yun Tae Lee ,  Bum Suk Kim ,  Tae Chan Kim ,  Jung Hoon Jung ,  Tae Sub Jung

IPC: H04N5/235 ,  H04N9/04 ,  H01L27/146 ,  H04N5/355

CPC classification number: H04N9/045 ,  H01L27/14603 ,  H04N5/35563

Abstract: An image sensor, an image processing apparatus including the same and an interpolation method of the image processing apparatus are provided. The image sensor includes a plurality of pixels that include a low-luminance pixel including a first photoelectric conversion device that accumulates a charge less than a predetermined reference value and a high-luminance pixel including a second photoelectric conversion device that accumulates a charge more than the predetermined reference value. Interpolation is carried out giving more weight to the low-luminance pixel at low luminance and giving more weight to the high-luminance pixel at high luminance, so that a higher SNR is obtained.

Abstract translation: 提供了图像传感器，包括该图像处理装置的图像处理装置和图像处理装置的内插方法。 图像传感器包括多个像素，其包括低亮度像素，该低亮度像素包括累积小于预定参考值的电荷的第一光电转换装置和包括第二光电转换装置的高亮度像素，该第二光电转换装置累积电荷多于 预定参考值。 对于低亮度的低亮度像素进行插值，对高亮度的高亮度像素赋予更多的权重，从而获得更高的信噪比。

公开(公告)号：US20130010162A1

公开(公告)日：2013-01-10

申请号：US13542921

申请日：2012-07-06

Applicant: Jung Chak Ahn ,  Yun Tae Lee ,  Bum Suk Kim ,  Tae Chan Kim ,  Jung Hoon Jung ,  Tae Sub Jung

Inventor： Jung Chak Ahn ,  Yun Tae Lee ,  Bum Suk Kim ,  Tae Chan Kim ,  Jung Hoon Jung ,  Tae Sub Jung

IPC: H04N9/68 ,  H01L27/146 ,  H04N5/335

CPC classification number: H04N9/045 ,  H01L27/14603 ,  H04N5/35563

Abstract: An image sensor, an image processing apparatus including the same and an interpolation method of the image processing apparatus are provided. The image sensor includes a plurality of pixels that include a low-luminance pixel including a first photoelectric conversion device that accumulates a charge less than a predetermined reference value and a high-luminance pixel including a second photoelectric conversion device that accumulates a charge more than the predetermined reference value. Interpolation is carried out giving more weight to the low-luminance pixel at low luminance and giving more weight to the high-luminance pixel at high luminance, so that a higher SNR is obtained.

Abstract translation: 提供了图像传感器，包括该图像处理装置的图像处理装置和图像处理装置的内插方法。 图像传感器包括多个像素，其包括低亮度像素，该低亮度像素包括累积小于预定参考值的电荷的第一光电转换装置和包括第二光电转换装置的高亮度像素，该第二光电转换装置累积电荷多于 预定参考值。 对于低亮度的低亮度像素进行插值，对高亮度的高亮度像素赋予更多的权重，从而获得更高的信噪比。

公开(公告)号：US08209527B2

公开(公告)日：2012-06-26

申请号：US12430722

申请日：2009-04-27

Applicant: Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F15/177

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F9/445 ,  G06F12/0638 ,  G06F15/177 ,  G06F2212/2022 ,  G11C8/16

Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

Abstract translation: 提供了具有第一处理器和第二处理器的数字处理的启动方法。 第一处理器和外部之间的接口被停止。 第二处理器程序代码从第一存储器发送到第二存储器。 用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。 第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。 第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

公开(公告)号：US08140935B2

公开(公告)日：2012-03-20

申请号：US13241343

申请日：2011-09-23

Applicant: Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

Inventor： Si-Hoon Hong ,  Yun-Tae Lee ,  Jun-Jin Kong

IPC: H03M13/00

CPC classification number: H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

公开(公告)号：US20120011416A1

公开(公告)日：2012-01-12

申请号：US13241343

申请日：2011-09-23

Applicant: Si-Hoon HONG ,  Yun-Tae LEE ,  Jun-Jin KONG

Inventor： Si-Hoon HONG ,  Yun-Tae LEE ,  Jun-Jin KONG

IPC: H03M13/05 ,  G06F11/10

CPC classification number: H03M13/2945 ,  G06F11/1072 ,  H03M13/09 ,  H03M13/136 ,  H03M13/1505 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/29 ,  H03M13/2906

Abstract: An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.

Abstract translation: 存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块， 根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块， ，第一ECC数据和第二ECC数据被存储在闪存设备中。

公开(公告)号：US20120011323A1

公开(公告)日：2012-01-12

申请号：US13234173

申请日：2011-09-16

Applicant: SUNG-JAE BYUN ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： SUNG-JAE BYUN ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F15/177

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F15/177 ,  G11C8/16 ,  Y02D10/13

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract translation: 多处理器系统包括第一处理器，与第一处理器通信的第二处理器，用于存储第一代码和第二代码以分别引导第一和第二处理器的第一非易失性存储器，可与第一处理器通信的第一存储器， 为第一处理器指定的第二易失性存储器，为第二处理器指定的第三易失性存储器，以及由第一和第二处理器共享的第四易失性存储器。

公开(公告)号：US08020081B2

公开(公告)日：2011-09-13

申请号：US11802334

申请日：2007-05-22

Applicant: Jun Jin Kong ,  Sung Chung Park ,  Yun Tae Lee ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun ,  Dong Ku Kang

Inventor： Jun Jin Kong ,  Sung Chung Park ,  Yun Tae Lee ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun ,  Dong Ku Kang

IPC: H03M13/03

CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/10

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a trellis coded modulation (TCM) modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract translation: 多级单元（MLC）存储器件可以包括：MLC存储器单元; 外部编码器，其使用第一编码方案对数据进行编码以生成外部编码比特流; 以及网格编码调制（TCM）调制器，其向MLC存储器单元施加编程脉冲以将数据写入MLC存储器单元。 可以通过对外部编码比特流进行TCM调制来生成编程脉冲。 一种在MLC存储器件中存储数据，从MLC存储器件读取数据或将数据存储在MLC存储器件中并从MLC存储器件读取数据的方法可以包括：使用第一编码方案对数据进行编码以产生外编码位流; 以及向MLC存储器件的MLC存储器单元施加编程脉冲以将数据写入MLC存储单元。 可以通过对外部编码比特流进行TCM调制来生成编程脉冲。

公开(公告)号：US20080137413A1

公开(公告)日：2008-06-12

申请号：US11802334

申请日：2007-05-22

Applicant: Jun Jin Kong ,  Sung Chung Park ,  Yun Tae Lee ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun ,  Dong Ku Kang

Inventor： Jun Jin Kong ,  Sung Chung Park ,  Yun Tae Lee ,  Young Hwan Lee ,  Si Hoon Hong ,  Jae Woong Hyun ,  Dong Ku Kang

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/10

Abstract: A multi-level cell (MLC) memory device may include: a MLC memory cell; an outer encoder that encodes data using a first encoding scheme to generate an outer encoded bit stream; and a TCM modulator that applies a program pulse to the MLC memory cell to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream. A method of storing data in a MLC memory device, reading data from the MLC memory device, or storing data in and reading data from the MLC memory device may include: encoding data using a first encoding scheme to generate an outer encoded bit stream; and applying a program pulse to a MLC memory cell of the MLC memory device to write the data in the MLC memory cell. The program pulse may be generated by TCM modulating the outer encoded bit stream.

Abstract translation: 多级单元（MLC）存储器件可以包括：MLC存储器单元; 外部编码器，其使用第一编码方案对数据进行编码以生成外部编码比特流; 以及将编程脉冲施加到MLC存储器单元以将数据写入MLC存储单元的TCM调制器。 可以通过对外部编码比特流进行TCM调制来生成编程脉冲。 一种在MLC存储器件中存储数据，从MLC存储器件读取数据或将数据存储在MLC存储器件中并从MLC存储器件读取数据的方法可以包括：使用第一编码方案对数据进行编码以产生外编码位流; 以及向MLC存储器件的MLC存储器单元施加编程脉冲以将数据写入MLC存储单元。 可以通过对外部编码比特流进行TCM调制来生成编程脉冲。