公开(公告)号：US09257467B2

公开(公告)日：2016-02-09

申请号：US12955287

申请日：2010-11-29

Applicant: Yun Tae Lee ,  Joon Seo Yim ,  Je Suk Lee ,  Jae Yong Park ,  Jun-Woo Park ,  Su-Young Lee

Inventor： Yun Tae Lee ,  Joon Seo Yim ,  Je Suk Lee ,  Jae Yong Park ,  Jun-Woo Park ,  Su-Young Lee

IPC: H01L27/146 ,  H04N5/225 ,  H04N5/345 ,  H04N9/04

CPC classification number: H04N5/23296 ,  H01L27/14618 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12044 ,  H04N5/2257 ,  H04N5/3454 ,  H04N5/374 ,  H04N5/378 ,  H04N9/045 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An image sensor module is provided. The image sensor module includes a printed circuit board (PCB), an image sensor chip disposed on a first plane of the PCB and electrically connected to the PCB, and an image signal processing chip disposed on the first plane of the PCB and electrically connected to the PCB. An aspect ratio of the image signal processing chip is at least two times greater than an aspect ratio of the image sensor chip. A minimum feature size of a metal line implemented in the image sensor chip is at least 1.5 times greater than a minimum feature size of a metal line implemented in the image signal processing chip.

Abstract translation: 提供图像传感器模块。 图像传感器模块包括印刷电路板（PCB），设置在PCB的第一平面上并电连接到PCB的图像传感器芯片，以及设置在PCB的第一平面上并且电连接到 PCB。 图像信号处理芯片的纵横比比图像传感器芯片的纵横比至少大两倍。 在图像传感器芯片中实现的金属线的最小特征尺寸比图像信号处理芯片中实施的金属线的最小特征尺寸至少大1.5倍。

公开(公告)号：US20110107076A1

公开(公告)日：2011-05-05

申请号：US12986264

申请日：2011-01-07

Applicant: Yong-Hoon KIM ,  Yun-Tae LEE ,  Sung-Up CHOI

Inventor： Yong-Hoon KIM ,  Yun-Tae LEE ,  Sung-Up CHOI

IPC: G06F9/24

CPC classification number: G06F9/4401

Abstract: An electronic information system comprises an external storage device and an application processor. The external storage device stores boot code and the application processor is adapted to receive the boot code from the external storage device and to perform a system booting operation during a power-up operation by executing the boot code.

Abstract translation: 电子信息系统包括外部存储装置和应用处理器。 外部存储装置存储引导代码，并且应用处理器适于从外部存储设备接收引导代码，并且在上电操作期间通过执行引导代码执行系统引导操作。

公开(公告)号：US07882344B2

公开(公告)日：2011-02-01

申请号：US11553201

申请日：2006-10-26

Applicant: Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F15/177

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F15/177 ,  G11C8/16 ,  Y02D10/13

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract translation: 多处理器系统包括第一处理器，与第一处理器通信的第二处理器，用于存储第一代码和第二代码以分别引导第一和第二处理器的第一非易失性存储器，可与第一处理器通信的第一存储器， 为第一处理器指定的第二易失性存储器，为第二处理器指定的第三易失性存储器，以及由第一和第二处理器共享的第四易失性存储器。

公开(公告)号：US20110007103A1

公开(公告)日：2011-01-13

申请号：US12835122

申请日：2010-07-13

Applicant: Bing Han ,  Paul Gallagher ,  Yun-tae Lee ,  Joon-seo Yim

Inventor： Bing Han ,  Paul Gallagher ,  Yun-tae Lee ,  Joon-seo Yim

IPC: G09G5/10

CPC classification number: G09G3/3406 ,  G09G2320/0626 ,  G09G2320/103 ,  G09G2340/16 ,  G09G2360/144

Abstract: An apparatus controls a backlight of a display panel of a camera system. The apparatus includes a sub-pixel extracting unit, an ambient light luminance calculating unit, and a backlight controller. The sub-pixel extracting unit extracts sub-pixel luminance values from image data, where the image data is indicative of a current image frame defined by a plurality of pixels, and where each of the pixels includes a plurality of sub-pixels. The ambient light luminance calculating unit calculates an ambient light luminance value of the current image frame from the sub-pixel luminance values extracted by the sub-pixel extracting unit. The backlight controller which generates a backlight control signal based on a comparison between the calculated ambient light luminance value of the current image frame and an ambient light luminance value of a previous image frame.

Abstract translation: 一种装置控制照相机系统的显示面板的背光。 该装置包括子像素提取单元，环境光亮度计算单元和背光控制器。 子像素提取单元从图像数据中提取子像素亮度值，其中图像数据表示由多个像素定义的当前图像帧，并且其中每个像素包括多个子像素。 环境光亮度计算单元从由子像素提取单元提取的子像素亮度值计算当前图像帧的环境光亮度值。 背光控制器，其基于计算出的当前图像帧的环境光亮度值与前一图像帧的环境光亮度值之间的比较来生成背光控制信号。

公开(公告)号：US20090210691A1

公开(公告)日：2009-08-20

申请号：US12430722

申请日：2009-04-27

Applicant: Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F15/177

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F9/445 ,  G06F12/0638 ,  G06F15/177 ,  G06F2212/2022 ,  G11C8/16

Abstract: A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

Abstract translation: 提供了具有第一处理器和第二处理器的数字处理的启动方法。 第一处理器和外部之间的接口被停止。 第二处理器程序代码从第一存储器发送到第二存储器。 用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。 第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。 第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

公开(公告)号：US20070240092A1

公开(公告)日：2007-10-11

申请号：US11692987

申请日：2007-03-29

Applicant: Yun-Tae Lee ,  Jong-Woo Park ,  Seon-Wook Hwang

Inventor： Yun-Tae Lee ,  Jong-Woo Park ,  Seon-Wook Hwang

IPC: G06F17/50 ,  H03K19/00

CPC classification number: H01L27/11807 ,  H01L24/73 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of fabricating a semiconductor integrated circuit, such as an ASIC, and a semiconductor integrated circuit using the same, are cost effective and allow lower non-recurring engineering compared with a platform ASIC by separately embodying a cell-based base block chip and a custom block chip of a gate array system and then combining both chips. When fabricating the semiconductor integrated circuit, formed by combining at least one standard function block with a newly-developed custom function block, the method of fabricating the semiconductor integrated circuit includes forming a base block chip that embodies the standard function block. Then, a custom block chip that embodies the custom function block is separately formed, and the base block chip is combined with the custom block chip.

Abstract translation: 制造诸如ASIC的半导体集成电路的方法以及使用该半导体集成电路的半导体集成电路的方法与平台ASIC相比，具有成本效益并且允许较低的非重复工程，通过单独实施基于单元的基块芯片和 门阵列系统的定制块芯片，然后组合两个芯片。 当制造通过将至少一个标准功能块与新开发的定制功能块组合而形成的半导体集成电路时，制造半导体集成电路的方法包括形成体现标准功能块的基块芯片。 然后，分别形成体现定制功能块的定制块芯片，并将基块芯片与定制块芯片组合。

公开(公告)号：US06976108B2

公开(公告)日：2005-12-13

申请号：US09773874

申请日：2001-01-31

Applicant: Youngsik Kim ,  Yun-Tae Lee

Inventor： Youngsik Kim ,  Yun-Tae Lee

IPC: G06F13/362 ,  G06F13/36 ,  G06F13/364 ,  G06F12/00

CPC classification number: G06F13/364

Abstract: A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.

Abstract translation: 芯片上的系统具有由至少一个系统总线容纳的功能块和用于容纳与外部块的通信的外部总线。 单个多管辖总线仲裁器具有可编程排名，用于为两个总线中的任一个的主站的请求分配优先级。 还提供了分配优先级的软件和方法。 对所需的哪些总线进行分析，然后分配优先级以最大化总线利用率，并提高芯片上的系统的速度。 另外，多管辖多通道直接存储器访问块可以是用于系统总线或外部总线的主块。

公开(公告)号：US08984237B2

公开(公告)日：2015-03-17

申请号：US13234173

申请日：2011-09-16

Applicant: Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

Inventor： Sung-Jae Byun ,  Young Min Lee ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

IPC: G06F12/00 ,  G06F12/06 ,  G06F9/44 ,  G06F15/177 ,  G11C8/16

CPC classification number: G06F12/0607 ,  G06F9/4405 ,  G06F15/177 ,  G11C8/16 ,  Y02D10/13

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract translation: 多处理器系统包括第一处理器，与第一处理器通信的第二处理器，用于存储第一代码和第二代码以分别引导第一和第二处理器的第一非易失性存储器，可与第一处理器通信的第一存储器， 为第一处理器指定的第二易失性存储器，为第二处理器指定的第三易失性存储器，以及由第一和第二处理器共享的第四易失性存储器。

公开(公告)号：US08462101B2

公开(公告)日：2013-06-11

申请号：US12835122

申请日：2010-07-13

Applicant: Bing Han ,  Paul Gallagher ,  Yun-tae Lee ,  Joon-seo Yim

Inventor： Bing Han ,  Paul Gallagher ,  Yun-tae Lee ,  Joon-seo Yim

IPC: G09G5/10

CPC classification number: G09G3/3406 ,  G09G2320/0626 ,  G09G2320/103 ,  G09G2340/16 ,  G09G2360/144

Abstract: An apparatus controls a backlight of a display panel of a camera system. The apparatus includes a sub-pixel extracting unit, an ambient light luminance calculating unit, and a backlight controller. The sub-pixel extracting unit extracts sub-pixel luminance values from image data, where the image data is indicative of a current image frame defined by a plurality of pixels, and where each of the pixels includes a plurality of sub-pixels. The ambient light luminance calculating unit calculates an ambient light luminance value of the current image frame from the sub-pixel luminance values extracted by the sub-pixel extracting unit. The backlight controller which generates a backlight control signal based on a comparison between the calculated ambient light luminance value of the current image frame and an ambient light luminance value of a previous image frame.

Abstract translation: 一种装置控制照相机系统的显示面板的背光。 该装置包括子像素提取单元，环境光亮度计算单元和背光控制器。 子像素提取单元从图像数据中提取子像素亮度值，其中图像数据表示由多个像素定义的当前图像帧，并且其中每个像素包括多个子像素。 环境光亮度计算单元从由子像素提取单元提取的子像素亮度值计算当前图像帧的环境光亮度值。 背光控制器，其基于计算出的当前图像帧的环境光亮度值与前一图像帧的环境光亮度值之间的比较来生成背光控制信号。

公开(公告)号：US08171378B2

公开(公告)日：2012-05-01

申请号：US12187427

申请日：2008-08-07

Applicant: Sung-Up Choi ,  Yun-Tae Lee ,  Sung-Man Hwang

Inventor： Sung-Up Choi ,  Yun-Tae Lee ,  Sung-Man Hwang

IPC: G06F11/00

CPC classification number: G06F11/1068 ,  G11B20/00086

Abstract: A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction code, and the flash memory includes a main area for storing the input data and a spare area for storing the encrypted first error correction code.

Abstract translation: 闪速存储器系统包括用于存储输入数据的闪速存储器和控制闪速存储器的存储器控​​制器，其中存储器控制器产生对应于输入数据的第一纠错码，并对第一纠错码进行加密，并且闪速存储器 包括用于存储输入数据的主区域和用于存储加密的第一纠错码的备用区域。