반도체 집적 회로 및 그 설계 방법
    31.
    发明公开
    반도체 집적 회로 및 그 설계 방법 审中-实审
    半导体集成电路及其设计方法

    公开(公告)号:KR1020130110961A

    公开(公告)日:2013-10-10

    申请号:KR1020120033345

    申请日:2012-03-30

    Inventor: 백상훈 서재우

    CPC classification number: G06F17/5081 G06F17/5068

    Abstract: PURPOSE: A semiconductor integrated circuit and a designing method thereof improve user convenience by reflecting the property change of a semiconductor device and quickly developing and providing various libraries. CONSTITUTION: At least one change is determined among the width and height of a semiconductor device and the space between the semiconductor devices (S510). A display layer displaying at least one semiconductor device is generated to change the width of the semiconductor device (S520). A new library is generated by applying the display layer generated on a produced layout (S530). The new library is verified (S540). The verified new library is provided to a customer who wants the same (S550). [Reference numerals] (AA) Start; (BB) End; (S510) Determine to change at least one out of the width and height of a semiconductor device and the space between the semiconductor devices; (S520) Generate a display layer; (S530) Generate a new library; (S540) Verify the new library; (S550) Provide the new library

    Abstract translation: 目的:一种半导体集成电路及其设计方法,通过反映半导体器件的性能变化并快速开发和提供各种库来提高用户便利性。 构成:在半导体器件的宽度和高度以及半导体器件之间的空间中确定至少一个变化(S510)。 产生显示至少一个半导体器件的显示层,以改变半导体器件的宽度(S520)。 通过应用在生成的布局上生成的显示层来生成新的库(S530)。 新图书馆经过验证(S540)。 验证的新图书馆提供给想要相同的客户(S550)。 (附图标记)(AA)开始; (BB)结束; (S510)确定改变半导体器件的宽度和高度中的至少一个以及半导体器件之间的空间; (S520)生成显示层; (S530)生成一个新的库; (S540)验证新库; (S550)提供新的库

Patent Agency Ranking