公开(公告)号：KR100546374B1

公开(公告)日：2006-01-26

申请号：KR1020030059834

申请日：2003-08-28

Applicant: 삼성전자주식회사

Inventor： 염근대

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 와이어와 반도체 칩간의 쇼트를 방지하면서 적층 형태로 구현할 수 있는 센터 패드를 갖는 적층형 반도체 패키지 및 그 제조방법을 개시한다. 개시된 본 발명의 적층형 반도체 패키지는, 적층된 적어도 하나의 단위 패키지 구조체를 포함한다. 단위 패키지 구조체는 인쇄 회로 기판과, 상기 인쇄 회로 기판상에 부착된 센터 패드형 반도체 칩을 포함한다. 상기 반도체 칩 상부에 상기 반도체 칩과 인쇄 회로 기판을 전기적으로 연결시키는 다수의 배선 패턴이 구비된 배선 기판이 부착되며,상기 인쇄 회로 기판의 뒷면에 상기 반도체 칩에 전기적 신호를 전달하는 외부 접속 단자가 부착된다. 이때, 상기 단위 패키지 구조체는 상기 하부의 단위 패키지 구조체의 배선 패턴과 상기 상부의 단위 패키지의 외부 접속 단자가 전기적으로 부착되도록 적층되어 있다.
센터 패드, 적층형, BGA, CSP

公开(公告)号：KR1020050023538A

公开(公告)日：2005-03-10

申请号：KR1020030059834

申请日：2003-08-28

Applicant: 삼성전자주식회사

Inventor： 염근대

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A multichip package with center pads and a method for manufacturing the same are provided to prevent short circuit between a wire and a semiconductor chip and to stack package structures with solder balls by attaching wiring boards with a plurality of wire patterns on each side of the top of a chip. CONSTITUTION: A center pad type semiconductor chip(130) is attached on a printed circuit board(120). A wiring board(140) is provided with a plurality of wiring patterns, the plurality of wiring patterns attached to the top of the semiconductor chip connect electrically the semiconductor chip with the printed circuit board. An external connection terminal attached on the back surface of the printed circuit board sends an electrical signal to the semiconductor chip.

Abstract translation: 目的：提供一种具有中心焊盘的多芯片封装及其制造方法，以防止电线和半导体芯片之间的短路，并通过在多个导线图案的每一侧上附加布线板来堆叠具有焊球的封装结构 芯片的顶部。 构成：中心焊盘型半导体芯片（130）安装在印刷电路板（120）上。 布线基板（140）具有多个布线图形，所述多个布线图形附着到所述半导体芯片的顶部，所述半导体芯片与所述印刷电路板电连接。 安装在印刷电路板的背面上的外部连接端子向半导体芯片发送电信号。

公开(公告)号：KR1020030040922A

公开(公告)日：2003-05-23

申请号：KR1020010071590

申请日：2001-11-17

Applicant: 삼성전자주식회사

Inventor： 염근대

IPC: H01L23/12

CPC classification number: H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PURPOSE: A chip scale package, manufacturing method thereof and stack chip scale package using the same are provided to enhance productivity by improving a staking structure of the chip scale package. CONSTITUTION: The first solder pad(217a) and the first connection pad(219a,) are formed on the first circuit forming part(210a). A semiconductor chip(201) having a plurality of bonding pads(203) is adhered to the first circuit forming part by adhesive members(220a,220b). The second circuit forming body(210b) includes the second connection pad(219b) and the second solder pad(217b). A plurality of bonding wires(240a,240b) are used for connecting electrically the bonding pads with the connections of the first and the second circuit forming parts. The bonding wires, the bonding pads, and connections pads are sealed with a sealing portion(205). A plurality of solder balls(230) are mounted on the solder pad.

Abstract translation: 目的：提供一种芯片级封装，其制造方法和使用其的堆叠芯片级封装，以通过改进芯片级封装的堆叠结构来提高生产率。 构成：第一焊盘（217a）和第一连接焊盘（219a）形成在第一电路形成部分（210a）上。 具有多个接合焊盘（203）的半导体芯片（201）通过粘合部件（220a，220b）粘接到第一电路形成部。 第二电路形成体（210b）包括第二连接焊盘（219b）和第二焊盘（217b）。 多个接合线（240a，240b）用于将接合焊盘与第一和第二电路形成部件的连接电连接。 接合线，接合焊盘和连接焊盘用密封部分（205）密封。 多个焊球（230）安装在焊盘上。

公开(公告)号：KR1020010081699A

公开(公告)日：2001-08-29

申请号：KR1020000007759

申请日：2000-02-18

Applicant: 삼성전자주식회사

Inventor： 송영재 ,  권영신 ,  염근대 ,  김영수

IPC: G06K19/00

CPC classification number: H01L23/055 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: PURPOSE: A memory card with high capacity is provided to increase the capacity of a memory card by increasing the number of a memory chip built-in a memory card without increasing the capacity of the memory chip or reducing the size of the memory chip. CONSTITUTION: A base card forms an external form of a memory card and combines 2 packages face to face. The first plate is equipped with the first surface in which external contact pads are formed, and the second surface in which the first contact pad electrically connected to the external contact pads are formed. The first package is mounted on the second surface. The second plate is equipped with the third surface which is exposed to an external part of the memory card and the fourth surface physically combined to the base card. The second package is mounted on the fourth surface. The first and the second contact pad are electrically connected to each connection unit.

Abstract translation: 目的：提供高容量的存储卡，通过增加存储卡内置存储芯片的数量来增加存储卡的容量，而不会增加存储芯片的容量或减小存储芯片的大小。 构成：基卡形成存储卡的外部形式，并面对面地组合2个包装。 第一板配备有形成外部接触焊盘的第一表面，并且形成与外部接触焊盘电连接的第一接触焊盘的第二表面。 第一个包装安装在第二个表面上。 第二板配备有暴露于存储卡的外部部分的第三表面和物理地组合到基卡的第四表面。 第二个包装安装在第四个表面上。 第一和第二接触垫电连接到每个连接单元。