Abstract:
PURPOSE: A ray tracing core and a ray tracing processing method are provided to prevent waste of a resource required in each unit, to monitor a ray tracing unit and a tree build unit, and to control the tree build unit. CONSTITUTION: A control unit monitors a load state of an RTU(Ray Tracing Unit) and a TBU(Tree Build Unit)(S310). The control unit controls to reduce the complexity of a spatial partitioning structure in case load of the RTU is greater than load of the TBU. The control unit controls to increase the complexity of the spatial partitioning structure in case load of the RTU is less than load of the TBU(S320). The control unit supplies the controlled complexity to the TBU(S330).
Abstract:
The present invention relates to a non-blocking texture cache memory system for a texture mapping pipeline and a method for operating a non-blocking texture cache memory. The texture cache memory includes a retry buffer which temporarily stores result data by a heat pipeline or a miss pipeline, a retry buffer lookup unit which looks up the retry buffer in response to a texture request transmitted from a processor, a checking unit which checks whether the result data corresponding to the texture request is stored in the retry buffer from the lookup result, and an output control unit which outputs the stored result data to the processor if the checking result shows that the result data corresponding to the texture request is stored.
Abstract:
A method and apparatus for providing shared caches are provided. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, tag bits and set index bits among bits of a memory address overlap each other as much as at least one bit. [Reference numerals] (110) First cache; (120) Second cache; (130) First comparison unit; (140) Second comparison unit; (150) Determination unit; (410) Third memory address; (412) Tag; (414) Set index; (416) Word; (AA) Hit or miss; (BB) Hit; (CC) Miss; (DD) Hit or miss; (EE,FF) Tag data; (GG) Address to an external memory; (HH) Data from the external memory
Abstract:
개시된 기술은 레이 트레이싱 코어에 관한 것으로, 시작 레벨 결정부 및 레벨 선택부를 포함한다. 시작 레벨 결정부는 시점과 종점으로 정의된 레이를 기초로 시작 레벨을 결정한다. 레벨 선택부는 결정된 시작 레벨에 대하여 노드 크로싱을 체크하여, 만일 노드 크로싱이 발생하면 노드 크로싱 수행 후 선택적 레벨 업을 수행한다. 따라서 개시된 기술은 피라미드 변위 맵의 탐색 시간을 줄일 수 있다.