Abstract:
The time switch interchanges 4096 time slots by making the clock frequency to be 8.192 MHz. The time switch includes a first and a second double port SRAM (1,2) having address moudles (AL,AR) for storing the audio information data on the corresponding addresses by time slot units, a control memory (3) for sending read address signal to the address module (AR), and a timing circuit (4) for sending write address signal to the address module (AL). The speed of the clock signal transmitted from the timing circuit to the address module (AL) is 8.192 MHz. The data reading from the SRAM (1,2) is sequencial process but the data writing on the RAM is random process.
Abstract:
k number of input means 16 having a plurality of series/parallel converters 17; a shared memory section 22 having k number of sub-shared memory section 32 connected to the input means 16; a control means 34 for controlling the shared memory 22; a demultiplexing means 20 for demultiplexing the output of the shared memory 22; and a plurality of parallel/series converting means 21 for converting the parallel output of the demultiplexing means 20 into a series data; a plurality of routing decoding means 35; a plurality of a first buffer means 36; a plurality of running-add network 39; multiple debanian network 40; a first multiplexing means 42; and a plurality of a phase address fool 37.
Abstract:
The generator for generating high precision pulse on the manual switch contact signal having bouncings comprises: a power-on reset circuit (1) to provide an initialization state at the power on; an OR gate (3) to control a set input of a flip-flop (4) corresponding to the input signal and a monitor circuit (6) signal; an AND gate (2) to control the flip-flop (4) reset input; the flip-flop (4) for generating a triggering pulse; a flip-flop (5) for retiming the trigger pulse to a clock pulse (CP); a monitor circuit (6) to control the input signal and the flip-flop (4) with a R.C. constant; a flip-flop (7) to delay the retimed trigger pulse for the CP period; an OR gate (8) to generate a pulse having a CP pulse width.
Abstract:
The time switch writes PCM data received from a multiplexer-demultiplexer (MDXA) on a communication memory and interchanges time slots. The time switch includes a first latch (1) for latching data income with speed of 8.192 Mbps by 8.192 clock signal, a parity checker (2) for detecting and correcting the parity fault in input data, a timing control circuit (9) for providing clock signal, a communication memory (3) for reading and writing the PCM data by counter output and random read address signal, a second latch (4) for latching the parallel data transmitted from the memory (3), a control memory interfacing unit (6) for receiving modes and addresses of a time switch processor (TSP) and sending corresponding data, and a circuit pack checker (11) for decoding circuit pack inspection bit to enable the latch (4) so that corresponding time slot data is transmitted.