타임 스위치
    31.
    发明授权
    타임 스위치 失效
    时间开关

    公开(公告)号:KR1019920001858B1

    公开(公告)日:1992-03-05

    申请号:KR1019890011511

    申请日:1989-08-12

    Abstract: The time switch interchanges 4096 time slots by making the clock frequency to be 8.192 MHz. The time switch includes a first and a second double port SRAM (1,2) having address moudles (AL,AR) for storing the audio information data on the corresponding addresses by time slot units, a control memory (3) for sending read address signal to the address module (AR), and a timing circuit (4) for sending write address signal to the address module (AL). The speed of the clock signal transmitted from the timing circuit to the address module (AL) is 8.192 MHz. The data reading from the SRAM (1,2) is sequencial process but the data writing on the RAM is random process.

    Abstract translation: 时钟开关通过使时钟频率为8.192 MHz来互换4096个时隙。 该时间切换器包括具有地址moudles(AL,AR)的第一和第二双端口SRAM(1,2),用于通过时隙单元在对应的地址上存储音频信息数据;控制存储器(3),用于发送读取地址 信号到地址模块(AR),以及定时电路(4),用于向地址模块(AL)发送写入地址信号。 从定时电路发送到地址模块(AL)的时钟信号的速度为8.192MHz。 来自SRAM(1,2)的数据读取是顺序处理,但RAM上的数据写入是随机过程。

    플로우 정보를 이용한 분산 반사 서비스 거부 공격 검출 장치 및 방법
    32.
    发明公开
    플로우 정보를 이용한 분산 반사 서비스 거부 공격 검출 장치 및 방법 审中-实审
    利用流量信息检测分布式反射拒绝服务攻击的装置和方法

    公开(公告)号:KR1020170102708A

    公开(公告)日:2017-09-12

    申请号:KR1020160025182

    申请日:2016-03-02

    CPC classification number: H04L63/1416 H04L43/0894 H04L63/1425 H04L63/1458

    Abstract: 본발명의일예와관련된분산반사서비스거부공격검출장치는통신망의일 지점을흐르는데이터의발신지의 IP, 발신지의포트번호, 수신지의 IP 및수신지의포트번호를포함하는플로우정보, 패킷수및 사이즈를획득하는모니터링부; 상기데이터의플로우정보, 패킷수및 사이즈가입력되는플로우테이블을저장하는메모리부; 및상기데이터의발신지포트번호및 수신지포트번호중 적어도하나가기 설정된포트번호인경우, 상기모니터링부에의해기 설정된시간동안획득된데이터의패킷수및 사이즈를플로우정보별로제 1 엔트리로써상기플로우테이블에입력하고, 상기제 1 엔트리의패킷수및 사이즈중 적어도하나와상기제 1 엔트리의플로우정보를이용하여 DRDoS 공격을검출하는제어부;를포함할수 있다.

    Abstract translation: 相关的IP,在网络源端口号中的一个点中流动的数据的源的本发明的一个示例性服务攻击检测装置的分布反射拒绝,目的地IP和流用于接收的信息包括一本杂志的端口号,数据包数量和尺寸 监视单元用于获取 存储单元,用于存储输入了数据的流信息,数据包的数量和大小的流表; 和流表作为第一条目,如果所述至少一个商店设置的源端口号的端口号,和该数据的接收jipoteu号,分组号和用于在设定的时间周期由监视单元由所述流信息中获得的数据的大小 输入,并且通过使用在所述第一条目中的第一条目控制单元的大小和分组的数目中的至少一个用于检测攻击DRDOS流的信息;可以含有。

    비대칭 제한적 공유메모리 비동기 전달모드(ATM:Asynchronous Transfef Mode) 스위치 장치
    33.
    发明授权
    비대칭 제한적 공유메모리 비동기 전달모드(ATM:Asynchronous Transfef Mode) 스위치 장치 失效
    具有非对称和约束通用存储器的ATM交换机

    公开(公告)号:KR1019960007674B1

    公开(公告)日:1996-06-08

    申请号:KR1019920026119

    申请日:1992-12-29

    Abstract: k number of input means 16 having a plurality of series/parallel converters 17; a shared memory section 22 having k number of sub-shared memory section 32 connected to the input means 16; a control means 34 for controlling the shared memory 22; a demultiplexing means 20 for demultiplexing the output of the shared memory 22; and a plurality of parallel/series converting means 21 for converting the parallel output of the demultiplexing means 20 into a series data; a plurality of routing decoding means 35; a plurality of a first buffer means 36; a plurality of running-add network 39; multiple debanian network 40; a first multiplexing means 42; and a plurality of a phase address fool 37.

    Abstract translation: k个输入装置16,具有多个串联/并行转换器17; 具有连接到输入装置16的k个共享存储器部分32的共享存储器部分22; 用于控制共享存储器22的控制装置34; 解复用装置20,用于解复用共享存储器22的输出; 以及多个并行/串联转换装置21,用于将解复用装置20的并行输出转换为串行数据; 多个路由解码装置35; 多个第一缓冲装置36; 多个运行添加网络39; 多个debanian网络40; 第一复用装置42; 以及多个相位地址傻瓜37。

    수동 리셋 스위치에 의한 고정밀 미세 단일 펄스 발생회로
    35.
    发明授权
    수동 리셋 스위치에 의한 고정밀 미세 단일 펄스 발생회로 失效
    用于手柄复位开关的脉冲发生器

    公开(公告)号:KR1019940002744B1

    公开(公告)日:1994-03-31

    申请号:KR1019910023158

    申请日:1991-12-17

    Abstract: The generator for generating high precision pulse on the manual switch contact signal having bouncings comprises: a power-on reset circuit (1) to provide an initialization state at the power on; an OR gate (3) to control a set input of a flip-flop (4) corresponding to the input signal and a monitor circuit (6) signal; an AND gate (2) to control the flip-flop (4) reset input; the flip-flop (4) for generating a triggering pulse; a flip-flop (5) for retiming the trigger pulse to a clock pulse (CP); a monitor circuit (6) to control the input signal and the flip-flop (4) with a R.C. constant; a flip-flop (7) to delay the retimed trigger pulse for the CP period; an OR gate (8) to generate a pulse having a CP pulse width.

    Abstract translation: 用于在具有整流的手动开关触点信号上产生高精度脉冲的发生器包括:上电复位电路(1),用于在通电时提供初始化状态; 用于控制对应于输入信号的触发器(4)的设定输入和监视电路(6)信号的或门(3); 用于控制触发器(4)复位输入的与门(2); 触发器(4),用于产生触发脉冲; 用于将触发脉冲重新定时到时钟脉冲(CP)的触发器(5); 一个用R.C.控制输入信号和触发器(4)的监视器电路(6)。 不变; 触发器(7),用于延迟CP周期的重新触发的触发脉冲; OR门(8),用于产生具有CP脉冲宽度的脉冲。

    타임스위치 통화메모리 장치
    40.
    发明授权
    타임스위치 통화메모리 장치 失效
    电话设备的时间开关对话

    公开(公告)号:KR1019920001860B1

    公开(公告)日:1992-03-05

    申请号:KR1019890011574

    申请日:1989-08-14

    Abstract: The time switch writes PCM data received from a multiplexer-demultiplexer (MDXA) on a communication memory and interchanges time slots. The time switch includes a first latch (1) for latching data income with speed of 8.192 Mbps by 8.192 clock signal, a parity checker (2) for detecting and correcting the parity fault in input data, a timing control circuit (9) for providing clock signal, a communication memory (3) for reading and writing the PCM data by counter output and random read address signal, a second latch (4) for latching the parallel data transmitted from the memory (3), a control memory interfacing unit (6) for receiving modes and addresses of a time switch processor (TSP) and sending corresponding data, and a circuit pack checker (11) for decoding circuit pack inspection bit to enable the latch (4) so that corresponding time slot data is transmitted.

    Abstract translation: 时间转换器将从多路复用器 - 解复用器(MDXA)接收的PCM数据写入通信存储器并交换时隙。 该时间开关包括用于通过8.192时钟信号锁定8.192Mbps速率的数据收入的第一锁存器(1),用于检测和校正输入数据中的奇偶校验故障的奇偶校验器(2),用于提供 时钟信号,用于通过计数器输出和随机读取地址信号读取和写入PCM数据的通信存储器(3),用于锁存从存储器(3)发送的并行数据的第二锁存器(4),控制存储器接口单元 6),用于接收时间交换处理器(TSP)的模式和地址并发送对应的数据;以及电路板检查器(11),用于解码电路组检查位以使锁存器(4)能够发送对应的时隙数据。

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