-
公开(公告)号：KR1020150057511A
公开(公告)日：2015-05-28
申请号：KR1020130140951
申请日：2013-11-19
Applicant: 한국전자통신연구원
CPC classification number: G01N33/22 , G01N21/3577 , G01N21/552 , G01N2201/08 , Y10T29/4913
Abstract: 광회로형유류검사센서장치가개시된다. 본발명의일 실시예에따른광 회로형유류검사센서장치는, 단파장을발생시키는광원부; 상기광원부에서발생된광신호를입력받아기준광신호와센싱신호를출력하는센서부; 상기기준광신호를입력받아기준광출력신호를출력하는제1 광검출부; 상기센싱신호를입력받아센싱광출력신호를출력하는제2 광검출부; 상기기준광출력신호와센싱광출력신호를입력받아연료의특성을판단하는연산제어부; 상기연산제어부의결과를받아출력하는출력부; 를포함한다.
Abstract translation: 公开了一种用于检查油的光电路式传感器装置。 根据本发明的实施例，用于检查油的光电路式传感器装置包括：产生短波长的光源单元; 传感器单元，接收在所述光源单元中产生的光信号，并输出参考光信号和感测信号; 第一光检测单元，接收参考光信号并输出参考光输出信号; 接收感测信号并输出感测光输出信号的第二光检测单元; 计算控制单元，接收参考光输出信号和感测光输出信号并确定燃料的特性; 以及输出单元，接收并输出计算控制单元的结果。
-
公开(公告)号：KR1020120072201A
公开(公告)日：2012-07-03
申请号：KR1020100134035
申请日：2010-12-23
Applicant: 한국전자통신연구원
IPC: G02B5/30
CPC classification number: B82Y30/00 , B82Y40/00 , G02B5/3058
Abstract: PURPOSE: A method for manufacturing a polarizing device is provided to simplify the manufacturing process of a polarizing device by forming an embossed pattern on a substrate, spreading conductive nano particles in the embossed pattern, and removing the extra nano particles to planarize the surface. CONSTITUTION: An embossed pattern(102) is formed on a substrate(101) by a nano imprinting process or e-beam lithography process. Conductive nano particles are spread on the overall surface of the embossed pattern. The overall surface of the embossed pattern with the conductive nano particles is planarized.
Abstract translation: 目的：提供一种用于制造偏振装置的方法，以通过在基底上形成压花图案来简化偏振装置的制造过程，在压纹图案中铺展导电纳米颗粒，以及除去额外的纳米颗粒以使表面平坦化。 构成：通过纳米压印工艺或电子束光刻工艺在衬底（101）上形成压花图案（102）。 导电纳米颗粒分散在压花图案的整个表面上。 具有导电纳米颗粒的压花图案的整个表面被平坦化。
-
公开(公告)号：KR101104251B1
公开(公告)日：2012-01-11
申请号：KR1020080116743
申请日：2008-11-24
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L21/027
Abstract: 본 발명은 반도체 장치의 제조 방법을 제공한다. 이 방법은 기판 상에 제 1 감광 패턴을 형성하는 것, 제 1 감광 패턴을 덮는 제 2 감광층 및 제 2 감광층을 덮는 제 3 감광층을 형성하는 것, 제 3 감광층을 패터닝하여 제 1 감광 패턴 상의 제 2 감광층의 일부를 노출하는 제 1 개구부를 갖는 제 3 감광 패턴을 형성하는 것, 제 1 개구부에 의해 노출된 제 2 감광층을 평탄화하여 제 1 감광 패턴을 노출하는 것, 노출된 제 1 감광 패턴을 제거하여 기판을 노출하는 제 2 개구부를 갖는 제 2 감광 패턴을 형성하는 것 및 제 2 개구부를 채우는 다리부 및 다리부와 연결되며 제 1 개구부에 한정되는 머리부를 갖는 티형 게이트 전극을 형성하는 것을 포함한다.
감광층, 게이트 전극, 광형상 반전 공정-
公开(公告)号：KR1020110073259A
公开(公告)日：2011-06-29
申请号：KR1020100122303
申请日：2010-12-02
Applicant: 한국전자통신연구원
CPC classification number: H01L51/5203 , H01L51/56 , H01L2251/56
Abstract: PURPOSE: An organic light emitting device and manufacturing method thereof are provided to adjust the interval between patterned metal electrodes, thereby maximizing light efficiency while light emitted from a light emitting layer passes between patterned metal electrodes. CONSTITUTION: A frontal electrode is coated on a substrate. A hole transfer layer(23) is coated on the frontal electrode and transfers a hole injected from the frontal electrode. A light emitting layer is coated on the hole transfer layer and emits light by combining the hole with an electron. An electron transfer layer(25) is coated on the light emitting layer and transfers an electron to the light emitting layer. A rear electrode(26) is coated on the electron transfer layer and injects an electron into the electron transfer layer. At least one of the frontal electrode and the rear electrode is formed by a patterned metal electrode so that light emitted from the light emitting layer is emitted between the patterned metal electrodes.
Abstract translation: 目的：提供一种有机发光器件及其制造方法，以调整图案化的金属电极之间的间隔，从而当从发光层发射的光通过图案化的金属电极之间时，光效达到最大。 构成：将正面电极涂覆在基材上。 空穴转移层（23）被涂覆在正面电极上，并传送从正面电极注入的空穴。 发光层涂覆在空穴转移层上，并通过将该孔与电子结合而发光。 电子转移层（25）涂覆在发光层上并将电子传递到发光层。 后电极（26）涂覆在电子转移层上，并将电子注入电子转移层。 正面电极和后电极中的至少一个由图案化的金属电极形成，使得从发光层发射的光在图案化的金属电极之间发射。
-
公开(公告)号：KR101042709B1
公开(公告)日：2011-06-20
申请号：KR1020080116745
申请日：2008-11-24
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
Abstract: 본 발명은 반도체 장치의 제조 방법을 제공한다. 이 방법은 기판 상에 제 1 감광 패턴을 형성하는 것, 제 1 감광 패턴을 덮으며 제 1 감광 패턴의 일부를 노출하는 제 2 감광 패턴을 형성하는 것, 제 2 감광 패턴 상에 제 1 감광 패턴과 제 1 감광 패턴의 주위의 제 2 감광층를 노출하는 제 1 개구부를 갖는 제 3 감광 패턴을 형성하는 것, 제 1 개구부에 의해 노출된 제 1 감광 패턴을 제거하여 기판을 노출하는 제 2 개구부를 형성하는 것 및 제 2 개구부를 채우는 다리부 및 다리부와 연결되며 제 1 개구부에 한정되는 머리부를 갖는 티형 게이트 전극을 형성하는 것을 포함한다.
감광층, 게이트 전극, 광형상 반전 공정-
Patent Agency Ranking
公开(公告)号：KR1020110048680A
公开(公告)日：2011-05-12
申请号：KR1020090105358
申请日：2009-11-03
Applicant: 한국전자통신연구원
IPC: H01L21/027
CPC classification number: G03F7/0002 , B82Y10/00 , B82Y40/00 , B29C59/022
Abstract: PURPOSE: Templates used for nano-imprint lithography and methods of fabricating the same are provided to implement a desired nano pattern and a micro pattern by easily controlling the dimension of an engraving nano pattern and an engraving micro pattern. CONSTITUTION: In templates used for nano-imprint lithography and methods of fabricating the same, laminated patterns(114a,118) are comprised of an engraving nano pattern(126) and engraving micro patterns(122,124) in a substrate. The substrate comprises glass, quartz, polycarbonate, and silicon. The substrate passes ultraviolet rays. The substrate having an engraving nano pattern thereon includes downhill slope from the surface. An etch stop layer(112) is interposed between the substrate and laminated patterns.
Abstract translation: 目的：提供用于纳米压印光刻的模板及其制造方法，以通过容易地控制雕刻纳米图案的尺寸和雕刻微图案来实现所需的纳米图案和微图案。 构成：在用于纳米压印光刻的模板及其制造方法中，叠层图案（114a，118）由雕刻纳米图案（126）和雕刻微图案（122,124）组成。 基板包括玻璃，石英，聚碳酸酯和硅。 基板通过紫外线。 其上具有雕刻纳米图案的基板包括来自表面的下坡。 蚀刻停止层（112）介于基板和叠层图案之间。
-
公开(公告)号：KR1020100073531A
公开(公告)日：2010-07-01
申请号：KR1020080132235
申请日：2008-12-23
Applicant: 한국전자통신연구원
IPC: H01L21/8238 , H01L21/336 , B82Y40/00
CPC classification number: H01L29/785 , H01L27/1292 , H01L29/41791 , H01L29/66795 , H01L51/0554
Abstract: PURPOSE: A self aligned field effect transistor structure is provided to increase operation speed by forming gate electrodes at both sides of an active area pattern and improving the operating characteristics of the device. CONSTITUTION: An active region pattern(132) is formed on a substrate(110). A first gate electrode(152a) and a second gate electrode(152b) are opposite to each other and the active region pattern is arranged between them. A source electrode(154a) and a drain electrode(154b) are connected to the active region pattern. The first and second gate electrodes and source and drain electrodes are arranged on the coplanar of the substrate. The first gate insulation pattern(144) surrounds the first gate electrode. The second gate insulting pattern(146) surrounds the second gate electrode.
Abstract translation: 目的：提供自对准场效应晶体管结构，通过在有源区域图案的两侧形成栅电极并提高器件的工作特性来提高工作速度。 构成：在衬底（110）上形成有源区域图案（132）。 第一栅电极（152a）和第二栅电极（152b）彼此相对，并且有源区图案布置在它们之间。 源极电极（154a）和漏极电极（154b）连接到有源区域图案。 第一和第二栅电极和源电极和漏极布置在基板的共面上。 第一栅极绝缘图案（144）围绕第一栅电极。 第二栅极绝缘图案围绕第二栅电极。
-
公开(公告)号：KR1020100058070A
公开(公告)日：2010-06-03
申请号：KR1020080116747
申请日：2008-11-24
Applicant: 한국전자통신연구원
IPC: H01L21/027 , H01L21/336
CPC classification number: G03F7/0002 , H01L21/0272
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to include a leg part and a head part of a T-shape gate electrode in order to fill openings. CONSTITUTION: A first photosensitive layer is formed on a substrate(100). A first photosensitive pattern is formed by performing an imprint lithography operation on the first photosensitive layer. A second photosensitive pattern, which covers the first photosensitive pattern, is formed. A third photosensitive pattern(132) with a first opening(134) is formed on the second photosensitive pattern. A second opening exposing the substrate is formed. A T-shape gate electrode(146) with a leg part(142) and a head part(144), which fill the second opening, is formed.
Abstract translation: 目的：提供一种半导体器件及其制造方法以包括T形栅电极的腿部和头部以填充开口。 构成：在基板（100）上形成第一感光层。 通过对第一感光层进行压印光刻操作来形成第一感光图案。 形成覆盖第一感光图案的第二感光图案。 具有第一开口（134）的第三感光图案（132）形成在第二感光图案上。 形成露出基板的第二开口。 形成有填充第二开口的具有腿部（142）和头部（144）的T形栅电极（146）。
-
公开(公告)号：KR1020100012657A
公开(公告)日：2010-02-08
申请号：KR1020080074170
申请日：2008-07-29
Applicant: 한국전자통신연구원
IPC: G02F1/136
CPC classification number: H01L29/78603 , G02F1/1368 , G03F7/0002
Abstract: PURPOSE: A thin film transistor and a manufacturing method thereof are provided to use an imprint mold, thereby patterning a gate insulating layer at the same time. CONSTITUTION: A semiconductor channel layer(120) and a gate insulating layer(130) are successively formed on the upper part of a substrate(110). The gate insulating layer is patterned in a wall shape by pressurizing an imprint mold(200) in which a recess pattern of the wall shape is formed on the gate insulating layer. A source electrode/a drain electrode and a gate electrode are formed at the same time by evaporating an electrode solution on both sides and the upper part of the gate insulating layer patterned in the wall shape. The imprint mold is made of elastomeric material with large elasticity.
Abstract translation: 目的：提供薄膜晶体管及其制造方法以使用压印模具，从而同时对栅绝缘层进行图案化。 构成：在衬底（110）的上部依次形成半导体沟道层（120）和栅极绝缘层（130）。 通过对在栅极绝缘层上形成有壁形状的凹部图案的压印模具（200）进行加压，将栅极绝缘层图案化成壁状。 通过蒸发壁形状的图案化的两侧的电极溶液和栅极绝缘层的上部，同时形成源电极/漏电极和栅电极。 压印模具由弹性大的弹性材料制成。
-
公开(公告)号：KR1020100012622A
公开(公告)日：2010-02-08
申请号：KR1020080074124
申请日：2008-07-29
Applicant: 한국전자통신연구원
IPC: H01L29/786 , H01L51/40
CPC classification number: H01L51/0558 , H01L51/0036 , H01L51/0533 , H01L51/0545 , H01L51/0529
Abstract: PURPOSE: A method for manufacturing an organic thin film transistor is provided to achieve a low turn-on voltage and minimize a leakage current by controlling the surface energy of a gate isolation layer. CONSTITUTION: A gate isolation layer(130) is formed on the top part of a gate electrode(120) in a substrate(110). A surface energy of a gate isolation layer is controlled. A semiconductor channel layer(150) on the top of the gate isolation layer formed by using a semiconductor material. A source electrode(160) and a drain electrode are formed in upper part of the semiconductor channel layer.
Abstract translation: 目的：提供一种用于制造有机薄膜晶体管的方法，以通过控制栅极隔离层的表面能来实现低导通电压并使漏电流最小化。 构成：在衬底（110）中的栅电极（120）的顶部上形成栅极隔离层（130）。 控制栅极隔离层的表面能。 通过使用半导体材料形成的栅极隔离层的顶部上的半导体沟道层（150）。 源电极（160）和漏电极形成在半导体沟道层的上部。
-
-
-
-
-
-
-
-
-
Search Results
162
records
(took 0.028 seconds)
