公开(公告)号：HK1020107A1

公开(公告)日：2000-03-10

申请号：HK99105296

申请日：1999-11-17

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00 ,  G11C

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

公开(公告)号：NO985933L

公开(公告)日：1999-02-22

申请号：NO985933

申请日：1998-12-17

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00 ,  G11C

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

公开(公告)号：NO990229D0

公开(公告)日：1999-01-19

申请号：NO990229

申请日：1999-01-19

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/22 ,  G11C16/28 ,  G11C

Abstract: A memory device includes a memory cell whose data state is sensed by a sense amplifier. A balance amplifier having the same construction as the sense amplifier is utilized to sense a balance cell having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit is used to adjust the conductivity of the of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.