公开(公告)号：EP0867070A4

公开(公告)日：1999-07-14

申请号：EP97909915

申请日：1997-09-30

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PAYNE JAMES E ,  PATHAK SAROJ

IPC: H01L21/8238 ,  G11C29/04 ,  H01L21/82 ,  H01L27/092 ,  H03K3/356 ,  H03K17/687

CPC classification number: H03K3/356008 ,  H03K3/356182

Abstract: A zero power fuse circuit includes a latch means (50) having two inputs, a first input (A) being latched to ground and a second input (B) being latched to Vcc. The latch means is triggered either by a momentary contact of the first input to ground or by the momentary contact of the second input to Vcc. A first embodiment includes two fuse element/capacitor pairs (F1, C1, F2, C2) each coupled to one of the two inputs (A, B) of the latch means. A second embodiment includes a pull-up transistor (20) and a fuse element/capacitor pair (F, C) coupled to the first and second inputs (A, B) respectively. A third embodiment includes a pull-down transistor (22) and a fuse element/capacitor pair (F, C) respectively coupled to the second and first inputs (A, B) of the latch means.

公开(公告)号：EP1034619A4

公开(公告)日：2003-09-10

申请号：EP98958071

申请日：1998-11-20

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).

公开(公告)号：EP0914660A4

公开(公告)日：2005-01-12

申请号：EP98918655

申请日：1998-04-24

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/22 ,  G11C16/28 ,  G11C7/06

CPC classification number: G11C16/22 ,  G11C16/28

Abstract: A memory device includes a memory cell (102) whose data state is sensed by a sense amplifier (100). A balance amplifier (200) having the same construction as the sense amplifier is utilized to sense a balance cell (202) having the same construction as the memory cell. The balance cell is maintained in a erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit (208) is used to adjust the conductivity of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

公开(公告)号：EP0914657A4

公开(公告)日：2001-10-04

申请号：EP98918604

申请日：1998-04-22

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00

CPC classification number: G11C16/24

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories (10). The bit line (35) voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

公开(公告)号：DE69840271D1

公开(公告)日：2009-01-08

申请号：DE69840271

申请日：1998-11-20

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: H03K17/22

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

公开(公告)号：NO20020847L

公开(公告)日：2002-02-21

申请号：NO20020847

申请日：2002-02-21

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PAYNE JAMES E ,  PATHAK JAGDISH

IPC: G11C7/06 ,  G11C7/14 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

公开(公告)号：NO20002194L

公开(公告)日：2000-07-24

申请号：NO20002194

申请日：2000-04-27

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: H03K17/22 ,  H03L7/00

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

公开(公告)号：DE60132088D1

公开(公告)日：2008-02-07

申请号：DE60132088

申请日：2001-05-14

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PAYNE JAMES E ,  PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/28 ,  G11C7/06 ,  G11C7/14 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

公开(公告)号：MY133776A

公开(公告)日：2007-11-30

申请号：MYPI9802212

申请日：1998-05-19

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ

IPC: G11C16/06 ,  G11C16/22 ,  G11C16/28

Abstract: A MEMORY DEVICE (FIG. 1) INCLUDES A MEMORY CELL (102) WHOSE DATA STATE IS SENSED BY A SENSE AMPLIFIER (100). A BALANCE AMPLIFIER (200) HAVING THE SAME CONSTRUCTION AS THE SENSE AMPLIFIER IS UTILIZED TO SENSE A BALANCE CELL (202) HAVING THE SAME CONSTRUCTION AS THE MEMORY CELL. THE BALANCE CELL IS MAINTAINED IN AN ERASED (CONDUCTIVE) STATE. THE BALANCE CELL IS GATED BY THE OUTPUT OF THE SENSE AMPLIFIER. SUCH A DEVICE OPERATES IN A WAY TO CONSUME THE SAME AMOUNT OF POWER REGARDLESS OF THE DATA STATE OF THE MEMORY CELL. IN ONE EMBODIMENT OF THE INVENTION, A MEMORY DEVICE CONSISTING OF A MEMORY ARRAY INCLUDES A BALANCE CIRCUIT ASSOCIATED WITH EACH OF THE SENSE AMPLIFIERS IN THE MEMORY DEVICE. IN ANOTHER EMBODIMENT OF THE INVENTION, A TRIM CIRCUIT (208) IS USED TO ADJUST THE CONDUCTIVITY OF THE BALANCE CIRCUIT. THIS ALLOWS THE BALANCE CIRCUIT TO BE FINE TUNED DURING MANUFACTURE TO COMPENSATE FOR PROCESS VARIATIONS, THUS ALLOWING THE BALANCE CIRCUIT TO BE MATCHED TO THE MEMORY CELLS.

公开(公告)号：MY116419A

公开(公告)日：2004-01-31

申请号：MYPI9801817

申请日：1998-04-23

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00

Abstract: THE PRESENT INVENTION RELATES TO A BIT LINE CLAMPING SCHEME FOR NON-VOLATILE MEMORIES (10). THE BIT LINE (35) VOLTAGE IS MAINTAINED AT A DESIRED VOLTAGE LEVEL SO AS TO AVOID READ DISTURB EFFECTS, WHILE BEING INDEPENDENT OF POWER SUPPLY VARIATIONS AND CONSUMING VIRTUALLY NO POWER. THE INVENTION MAKES PRACTICAL MEMORY DEVICES WHICH ARE DESIGNED FOR BOTH HIGH VOLTAGE (5 VOLT) OPERATION AND LOW VOLTAGE (3.3 AND 2.5 VOLT) OPERATION. (FIG 1)