中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.049 seconds)

    Scheduler and CPU performance controller cooperation
    32.
    发明授权
    Scheduler and CPU performance controller cooperation 有权

    公开(公告)号：US10437639B2

    公开(公告)日：2019-10-08

    申请号：US15786466

    申请日：2017-10-17

    Applicant: Apple Inc.

    Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  John Dorsey ,  Bryan Hinch ,  Cyril De La Cropte De Chanterac ,  Oliver Cozette

    IPC: G06F9/48 ,  G06F9/52

    Abstract: In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.

    Hand-off scheduling
    34.
    发明授权
    Hand-off scheduling 有权

    公开(公告)号：US10310891B2

    公开(公告)日：2019-06-04

    申请号：US14871837

    申请日：2015-09-30

    Applicant: Apple Inc.

    Inventor： Daniel A. Chimene ,  Daniel A. Steffen ,  James M Magee ,  Russell A. Blaine ,  Shantonu Sen

    IPC: G06F9/48 ,  G06F9/50 ,  G06F9/46

    Abstract: Disclosed herein are systems, methods, and computer-readable media directed to scheduling threads in a multi-processing environment that can resolve a priority inversion. Each thread has a scheduling state and a context. A scheduling state can include attributes such as a processing priority, classification (background, fixed priority, real-time), a quantum, scheduler decay, and a list of threads that may be waiting on the thread to make progress. A thread context can include registers, stack, other variables, and one or more mutex flags. A first thread can hold a resource with a mutex, the first thread having a low priority. A second thread having a scheduling state with a high priority can be waiting on the resource and may be blocked behind the mutex held by the first process. A scheduler can execute the context of the lower priority thread using the scheduler state of the second, higher priority thread. More than one thread can be waiting on the resource held by the first thread. A “pusher list” of threads that are waiting on the first thread can be associated with the first thread. The scheduler can use the pusher list to identify threads that need the first thread to make progress until the first thread releases the resource and mutex. Then, the scheduler can use the pusher list to identify threads that are now runnable and make immediate use of the resource.

    MULTI-THREAD SYNCHRONIZATION PRIMITIVE
    35.
    发明申请
    MULTI-THREAD SYNCHRONIZATION PRIMITIVE 审中-公开

    公开(公告)号：US20180349209A1

    公开(公告)日：2018-12-06

    申请号：US15836459

    申请日：2017-12-08

    Applicant: Apple Inc.

    Inventor： Daniel A. Steffen ,  Pierre Habouzit ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  James M. Magee ,  Puja Gupta

    IPC: G06F9/52 ,  G06F9/48

    Abstract: Techniques are disclosed relating to efficiently handling execution of multiple threads to perform various actions. In some embodiments, an application instantiates a queue and a synchronization primitive. The queue maintains a set of work items to be operated on by a thread pool maintained by a kernel. The synchronization primitive controls access to the queue by a plurality of threads including threads of the thread pool. In such an embodiment, a first thread of the application enqueues a work item in the queue and issues a system call to the kernel to request that the kernel dispatch a thread of the thread pool to operate on the first work item. In various embodiments, the dispatched thread is executable to acquire the synchronization primitive, dequeue the work item, and operate on it.

    SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE CONTROLLER AND DEFERRED INTER-PROCESSOR INTERRUPTS
    37.
    发明申请
    SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE CONTROLLER AND DEFERRED INTER-PROCESSOR INTERRUPTS 审中-公开

    公开(公告)号：US20180349177A1

    公开(公告)日：2018-12-06

    申请号：US15870770

    申请日：2018-01-12

    Applicant: Apple Inc.

    Inventor： Constantin Pistol ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  Russell A. Blaine ,  Kushal Dalmia

    IPC: G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

    Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

Patent Agency Ranking