公开(公告)号：US20220148249A1

公开(公告)日：2022-05-12

申请号：US17103462

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Yoong Chert Foo ,  Ali Rabbani Rankouhi ,  Justin A. Hensley ,  Jonathan M. Redshaw

IPC: G06T15/00 ,  G06F9/50 ,  G06F9/38 ,  G06T1/60

Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

公开(公告)号：US20220036638A1

公开(公告)日：2022-02-03

申请号：US17103406

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T15/00

Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

公开(公告)号：US11113788B2

公开(公告)日：2021-09-07

申请号：US17001007

申请日：2020-08-24

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Ralph C. Taylor ,  Randall R. Rauwendaal ,  Jonathan M. Redshaw

IPC: G06T3/40 ,  G06T15/40 ,  G06F30/30 ,  G06F3/01 ,  G06T15/00 ,  G06T15/60 ,  G06F119/18

Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.

公开(公告)号：US20210004331A1

公开(公告)日：2021-01-07

申请号：US17027271

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Ramani ,  Fang Liu ,  Steven Fishwick ,  Jonathan M. Redshaw

IPC: G06F12/0888 ,  G06F12/0815 ,  G06F12/0877

Abstract: Techniques are disclosed relating to filtering cache accesses. In some embodiments, a control unit is configured to, in response to a request to process a set of data, determine a size of a portion of the set of data to be handled using a cache. In some embodiments, the control unit is configured to determine filtering parameters indicative of a set of addresses corresponding to the determined size. In some embodiments, the control unit is configured to process one or more access requests for the set of data based on the determined filter parameters, including: using the cache to process one or more access requests having addresses in the set of addresses and bypassing the cache to access a backing memory directly, for access requests having addresses that are not in the set of addresses. The disclosed techniques may reduce average memory bandwidth or peak memory bandwidth.

公开(公告)号：US10783085B1

公开(公告)日：2020-09-22

申请号：US16290646

申请日：2019-03-01

Applicant: Apple Inc.

Inventor： Karthik Ramani ,  Fang Liu ,  Steven Fishwick ,  Jonathan M. Redshaw

IPC: G06F12/0888 ,  G06F12/0815 ,  G06F12/0877

Abstract: Techniques are disclosed relating to filtering cache accesses. In some embodiments, a control unit is configured to, in response to a request to process a set of data, determine a size of a portion of the set of data to be handled using a cache. In some embodiments, the control unit is configured to determine filtering parameters indicative of a set of addresses corresponding to the determined size. In some embodiments, the control unit is configured to process one or more access requests for the set of data based on the determined filter parameters, including: using the cache to process one or more access requests having addresses in the set of addresses and bypassing the cache to access a backing memory directly, for access requests having addresses that are not in the set of addresses. The disclosed techniques may reduce average memory bandwidth or peak memory bandwidth.

公开(公告)号：US20190102865A1

公开(公告)日：2019-04-04

申请号：US16130265

申请日：2018-09-13

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Ralph C. Taylor ,  Randall R. Rauwendaal ,  Jonathan M. Redshaw

IPC: G06T3/40 ,  G06T15/60 ,  G06F17/50 ,  G06F3/01 ,  G06T15/00

Abstract: Techniques are disclosed relating to rendering graphics objects. In some embodiments, a graphics unit is configured to transform graphics objects from a virtual space into a second space according to different transformation parameters for different portions of the second space. This may result in sampling different portions of the virtual space at different sample rates, which may reduce the number of samples required in various stages of the rendering process. In the disclosed techniques, transformation may occur prior to rasterization and shading, which may further reduce computation and power consumption in a graphics unit, improve image quality as displayed to a user, and/or reduce bandwidth usage or latency of video content on a network. In some embodiments, a transformed image may be viewed through a distortion-compensating lens or resampled prior to display.