中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.03 seconds)

    Cache control to preserve register data
    6.
    发明授权
    Cache control to preserve register data 有权

    公开(公告)号：US12182037B2

    公开(公告)日：2024-12-31

    申请号：US18173500

    申请日：2023-02-23

    Applicant: Apple Inc.

    Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

    IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/0891

    Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

    Graphics memory space for shader core
    9.
    发明授权
    Graphics memory space for shader core 有权

    公开(公告)号：US11521343B2

    公开(公告)日：2022-12-06

    申请号：US17103462

    申请日：2020-11-24

    Applicant: Apple Inc.

    Inventor： Terence M. Potter ,  Yoong Chert Foo ,  Ali Rabbani Rankouhi ,  Justin A. Hensley ,  Jonathan M. Redshaw

    IPC: G06F15/16 ,  G06T15/06 ,  G06T15/00 ,  G06F9/48 ,  G06F9/50 ,  G06T1/20 ,  G06F16/22 ,  G06F30/31 ,  G06F9/38 ,  G06T1/60 ,  G06T17/10 ,  G16H40/67 ,  G06Q10/10 ,  G06Q50/04

    Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.

    Ray Intersect Circuitry with Parallel Ray Testing
    10.
    发明申请
    Ray Intersect Circuitry with Parallel Ray Testing 有权

    公开(公告)号：US20220036639A1

    公开(公告)日：2022-02-03

    申请号：US17103433

    申请日：2020-11-24

    Applicant: Apple Inc.

    Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

    IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

    Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.

Patent Agency Ranking