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公开(公告)号：CA2312349A1
公开(公告)日：2000-12-22
申请号：CA2312349
申请日：2000-06-21
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
Abstract: A charge pump (2) is supplied to reset in rated conditions the error signal of a phase-locked loop of the type whereby a phase detector (1) periodically supplies this pump (2) with a first and second impulse having emission instants dependent on the phase ratio between phase-locked loop input signals and are allocated to control circuit output increase or decrease respectively by means of ring filter (3a, 3b). The pump features loops (21, 22, 23, 24, 28) to transform the first and second impulse into a first and second voltage signal of longer duration than maximum impulse duration and featuring values the difference of which depends on the phase ratio between the loop input signals and to generate a signal in a current representative of such difference.
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公开(公告)号：CA2171690C
公开(公告)日：2000-07-18
申请号：CA2171690
申请日：1996-03-13
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO
Abstract: A circuit for clock signal extraction from a high speed data stream for providing rapid locking with the input data stream and a locally generated clock signal. The circuit is suitable for fabrication in a CMOS digital integrated circuit, and features low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.
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公开(公告)号：CA2284956A1
公开(公告)日：2000-04-05
申请号：CA2284956
申请日：1999-10-04
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
Abstract: A current reference generator comprises a pair of identical units (G1, G2) which generate respective current references (11, 12), and a circuit (CL) for the linear combination of the two references. In each of the two units, the elements (S1, S2) which, by their current-voltage characteristics, determine the working point comprise respectively a single transistor (T1) and a pair of transistors (T2, T3), of the same type as the first, connected in series. A differential amplifier (AD) maintains stable the working point of the respective unit as power supply voltage varies.
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公开(公告)号：IT1295950B1
公开(公告)日：1999-05-28
申请号：ITTO970970
申请日：1997-11-06
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO
Abstract: The loop comprises an oscillator (5), usually made as a voltage controlled oscillator (VCO), arranged to operate selectively according to different input/output characteristics. The circuit further comprises means (81) to selectively control the operation of the oscillator (5) thereby making the oscillator (5) itself operate on one of said characteristics selectively determined according to the operating conditions of the loop (1).
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公开(公告)号：ITTO981035D0
公开(公告)日：1998-12-11
申请号：ITTO981035
申请日：1998-12-11
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , BALISTRERI EMANUELE
Abstract: The circuit comprises an input comparator (2) capable of generating a deviation signal which can be used for driving an oscillator (5) so as to generate an output signal (CLKOUT) locked to the input signal. The oscillator (5) can operate according to a plurality of characteristics under the control of control means (8) comprising searching means arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator (5) by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional means of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.
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Patent Agency Ranking
公开(公告)号：IT1279165B1
公开(公告)日：1997-12-04
申请号：ITTO950190
申请日：1995-03-14
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO
Abstract: The circuit for clock signal extraction from a high speed data stream allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit comprises a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase, and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.
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公开(公告)号：CA2290723C
公开(公告)日：2003-10-07
申请号：CA2290723
申请日：1999-11-25
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
IPC: H01L21/822 , H01L27/04 , H03F3/45 , H03H11/26 , H03K3/0231 , H03K3/03 , H03K3/354 , H03K5/13
Abstract: The delay element consists of a differential amplifier (M15, M8, M2, M6, M5) in which the load transistors (M2, M5) are associated to respective gate biasing transistors (M21, M22) connected in a source follower configuration, and to feedback transistors (M3, M4), which implement a negative impedance in parallel to a positive impedance represented by each of the load transistors (M2, M5). The modulation of the delay is achieved by modulating the bias currents of the load transistors (M2, M5), the feedback transistors (M3, M4) and the gate biasing transistors (M21, M22).
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公开(公告)号：CA2284956C
公开(公告)日：2003-08-12
申请号：CA2284956
申请日：1999-10-04
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
Abstract: A current reference generator comprises a pair of identical units (G1, G2) which generate respective current references (11, 12), and a circuit (CL) for the linear combination of the two references. In each of the two units, the elements (S 1, S2) which, by their current-voltage characteristics, determine the working point comprise respectively a single transistor (T1) and a pair of transistors (T2, T3), of the same type as the first, connected in series. A differential amplifier (AD) maintains stable the working point of the respective unit as power supply voltage varies.
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公开(公告)号：CA2292042C
公开(公告)日：2002-08-13
申请号：CA2292042
申请日：1999-12-10
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
Abstract: A phase locked loop comprising an input comparator capable of generating a deviation signal which is used for driving an oscillator so as to generate an output signal locked to the input signal. The oscillator operates according to a plurality of characteristics under the control of control means comprising searching means arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional means of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.
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公开(公告)号：IT1308744B1
公开(公告)日：2002-01-10
申请号：ITTO990532
申请日：1999-06-22
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BALISTRERI EMANUELE , BURZIO MARCO
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