公开(公告)号：JPH10117033A

公开(公告)日：1998-05-06

申请号：JP11862297

申请日：1997-04-23

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO ,  LUKA PESAND

IPC: H01L27/092 ,  H01L21/8238 ,  H01S5/042 ,  H01S5/068 ,  H01S5/40 ,  H04B10/04 ,  H04B10/06 ,  H04B10/142 ,  H04B10/152 ,  H01S3/133

Abstract: PROBLEM TO BE SOLVED: To provide a drive circuit allowing drive light sources of both conduction types and allowing operation not substantially depending on a manufacturing process. SOLUTION: This circuit consists of a bias and modulation current generator and a pair of control voltage sources to this bias and modulation current generator. The control voltage sources B, M obtain a control voltage pair from a drive current. The generator which the light source LA requires can be selected by an outside signal by using control logic and a CMOS gate. This circuit can be prepared by using three pads consisting of an integrated circuit. As these pads, there are those having respective control voltage sources B, M and the thirds D consisting of the current generator, the MOS gate and the control logic.

公开(公告)号：JP2000187517A

公开(公告)日：2000-07-04

申请号：JP34181199

申请日：1999-12-01

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: H01L21/8238 ,  G05F3/24 ,  H01L27/02 ,  H01L27/092 ,  H03B5/04 ,  H03F1/30 ,  H03K19/003

Abstract: PROBLEM TO BE SOLVED: To provide a device for compensating the fluctuation of a process and of an operation parameter in a CMOS integrated circuit. SOLUTION: This device includes means (CP and CT) for generating 1st and 2nd compensation signals. These compensation signals depend on the quality index of a manufacturing process and the operation temperature of P type and N type transistors of an integrated circuit and also can compensate variation from prescribed value of quantity to be controlled. The deviation occurs because the quality index and the temperature deviate from central value generating desired output parameter value. Also, a compensating device can preferably be realized in the form of a CMOS integrated circuit together with a device (OS) to be compensated.

公开(公告)号：JP2000183734A

公开(公告)日：2000-06-30

申请号：JP35030499

申请日：1999-12-09

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/107

Abstract: PROBLEM TO BE SOLVED: To provide a phase locked loop that is configured to be in operation according to a plurality of characteristics flexibly with high reliability over a sufficiently wide frequency range. SOLUTION: The phase locked loop includes an input comparator 2 that generates a deviation signal, and the deviation signal is used to drive an oscillator 5 to generate an output signal (CLKOUT) locked to an input signal. The oscillator 5 is operated according to a plurality of characteristics under the control of a control means 8 including a search means. The search means executes a 1st search stage for a characteristic group where an operation of the oscillator 5 is allowed by scanning the range that can gradually be reduced according to a general binary search procedure. When the 1st search step is finished, other fine search means identifies an optimum operating point to automatically compensate the fluctuation that may be possible.

公开(公告)号：JPH11225070A

公开(公告)日：1999-08-17

申请号：JP32440098

申请日：1998-10-30

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO

IPC: H03K5/26 ,  H03K3/027 ,  H03K3/03 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To obtain a high performance phase locked loop circuit. SOLUTION: This phase locked loop circuit includes an oscillator 5, which is usually configured as a voltage controlled oscillator VCO and is operated selectively according to different input/output characteristics. The phase locked loop circuit further includes a means 81 that selectively control the operation of the oscillator 5 under any of the input/output characteristics determined selectively according to the operating state of the phase locked loop 1.

公开(公告)号：JP2001044828A

公开(公告)日：2001-02-16

申请号：JP2000188102

申请日：2000-06-22

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  BALISTRERI EMANUELE

IPC: H03L7/093 ,  H03L7/089

Abstract: PROBLEM TO BE SOLVED: To provide a charging pump which does not require giving very short impulses to a ring filter and an oscillator. SOLUTION: A phase detector (1) of the phase-locked loop gives 1st and 2nd impulses to a charge pump (2) periodically, the impulses have an emission time, depending on a phase ratio of input signals of the phase-locked loop and ring filters (3a, 3b) respectively control increase or decrease in the circuit output. The charging pump 2 is a loop (21, 22, 23, 24, 28), converts the 1st and 2nd impulses into 1st and 2nd voltage signals with a longer duration than the maximum impulse duration and characteristic values, whose difference depends on a phase ratio of the loop input signals and generates a signal with a current denoting this difference.

公开(公告)号：JP2000165201A

公开(公告)日：2000-06-16

申请号：JP33277299

申请日：1999-11-24

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: H01L21/822 ,  H01L27/04 ,  H03F3/45 ,  H03H11/26 ,  H03K3/0231 ,  H03K3/03 ,  H03K3/354 ,  H03K5/13

Abstract: PROBLEM TO BE SOLVED: To obtain the method for extending a tuning available range of a CMOS(complementary metal oxide semiconductor) delay element, based on a differential amplifier and also obtain the delay element with the tuning available range extended by this method. SOLUTION: The delay element comprises a differential amplifier (M15, M8, M2, M6, M5), and load transistors(TRs) (M2, M5) are connected to gate bias TRs (M21, M22) connected in a source follower configuration and also connected to feedback TRs (M3, M4) that achieve a load impedance in parallel with a positive impedance represented by the load TRs (M2, M5). Modulation by the delay element is attained by modulating a bias current of the load TRs (M2, M5), the feedback TRs (M3, M4) and the gate bias TRs (M21, M22).

公开(公告)号：JP2000122740A

公开(公告)日：2000-04-28

申请号：JP28288799

申请日：1999-10-04

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: G05F3/24 ,  G05F3/26 ,  H03F1/30 ,  H03L7/089

Abstract: PROBLEM TO BE SOLVED: To provide a reference current generation circuit independent of not only changes in power supply voltage and temperature but also technical processes. SOLUTION: A reference current generator includes a pair of identical units G1, G2 for generating respective reference currents and a circuit CL for linearly connecting two references. Each of elements S1, S2 for determining respective operation points by current-voltage characteristics in respective units G1, G2 includes a single transistor(TR) T1 and a pair of TRs T2, T3 belonging to the same type as the TR T1 and connected in series. A differential amplifier AD stably maintains the operation points of respective units G1, G2 when power supply voltage is changed.

公开(公告)号：JPH1091578A

公开(公告)日：1998-04-10

申请号：JP21547897

申请日：1997-07-28

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BOSTICA BRUNO ,  BURZIO MARCO ,  PELLEGRINO PAOLO

IPC: G06F13/42 ,  H03K5/00 ,  H03K5/13 ,  H04L7/02 ,  H04L7/033

Abstract: PROBLEM TO BE SOLVED: To provide a device and a method to secure the time alignment of two digital signals which are substantially isochronal to each other. SOLUTION: Plural (2 ) pieces of replicas CK1 to CK4 are produced for a 1st signal CKIN having a given phase difference, and the replicas CK3 and CK4 are sampled (4, 5) in response to the rise edge of a 2nd signal DATA. A combination of logical signals is obtained through the above sampling and shows the phase relation between each of replicas CK1 to CK4 and the signal DATA. The output signal CKOIJT of this device is aligned with the signal DATA and corresponds to one of replicas CK1 to CK4 of the signal CKIN that reproduces best the desired alignment condition.

公开(公告)号：CA2212292C

公开(公告)日：2001-10-16

申请号：CA2212292

申请日：1997-07-30

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  BOSTICA BRUNO ,  PELLEGRINO PAOLO

IPC: G06F13/42 ,  H03K5/00 ,  H03K5/13 ,  H04L7/02 ,  H04L7/033

Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.

公开(公告)号：CA2291540A1

公开(公告)日：2000-06-03

申请号：CA2291540

申请日：1999-12-03

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: G05F3/24 ,  H01L23/00 ,  H01L23/34 ,  H01L27/02 ,  H03H11/02

Abstract: A device is provided for compensating process and operating parameters variations in a CMOS integrated circuit . The device comprises means for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device to be subjected to compensation.