公开(公告)号：IT7868269D0

公开(公告)日：1978-06-02

申请号：IT6826978

申请日：1978-06-02

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MELINDO FLAVIO

IPC: H04Q3/72 ,  H04M19/00 ,  H04M

Abstract: The two talking wires of a line loop extending from a subscriber station to a central office, provided with respective blocking capacitors, are connected on the subscriber side of these blocking capacitors to respective signal detectors fed from a common battery and cross-coupled by a common compensating capacitor. The two signal detectors receive outgoing signals from the central-office equipment via a common photoelectric coupler and transmit incoming signals to that equipment by way of respective bistable threshold comparators and individal photoelectric couplers. The two signal detectors with their threshold comparators are constituted in integrated circuity by mutually complementary transistors and diodes together with associated resistors.

公开(公告)号：DE2443526A1

公开(公告)日：1975-04-17

申请号：DE2443526

申请日：1974-09-11

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MELINDO FLAVIO ,  PERUCCA GIOVANNI

IPC: H04Q11/04

Abstract: A PCM/TDM terminal has m parallel receiving lines and m parallel transmitting lines for recurrent sequences of n words, of m bits each, originating at or destined for n channels connectable to that terminal by way of two alternately operating conversion units. Each conversion unit comprises an orthogonal matrix of m.n register stages for individual bits, divided into m columns and n rows, the first unit communicating with the channels while the second unit communicates with the terminal and vice versa. In an alternation of switching phases whose duration equals the time period occupied by an m-bit word serially arriving or departing over any channel, the unit communicating with the channels has its n row inputs and its n row outputs respectively connected to the incoming and outgoing channel branches while the unit communicating with the terminal has its m column inputs and its m column outputs respectively connected to the transmitting and receiving terminal lines. Thus, in a first phase the first unit stores in its n rows the bits of as many words arriving over the incoming channel branches and, simultaneously, reads out to the outgoing channel branches the bits of n words previously receiving from the terminal; at the same time the second unit stores in its m columns the bits of n successive words coming from the terminal and reads out to the terminal the bits of as many words previously fed in by the channels. In a second phase the roles of the two units are reversed.

公开(公告)号：DE2414624A1

公开(公告)日：1974-11-07

申请号：DE2414624

申请日：1974-03-26

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MELINDO FLAVIO

IPC: H03G3/20 ,  H04B3/04 ,  H04J3/14 ,  H03K13/00 ,  H04J3/02