公开(公告)号：US3914553A

公开(公告)日：1975-10-21

申请号：US50861274

申请日：1974-09-23

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MELINDO FLAVIO ,  PERUCCA GIOVANNI

IPC: H04Q11/04 ,  H04J3/00

CPC classification number: H04Q11/04

Abstract: A PCM/TDM terminal has m parallel receiving lines and m parallel transmitting lines for recurrent sequences of n words, of m bits each, originating at or destined for n channels connectable to that terminal by way of two alternately operating conversion units. Each conversion unit comprises an orthogonal matrix of m.n register stages for individual bits, divided into m columns and n rows, the first unit communicating with the channels while the second unit communicates with the terminal and vice versa. In an alternation of switching phases whose duration equals the time period occupied by an m-bit word serially arriving or departing over any channel, the unit communicating with the channels has its n row inputs and its n row outputs respectively connected to the incoming and outgoing channel branches while the unit communicating with the terminal has its m column inputs and its m column outputs respectively connected to the transmitting and receiving terminal lines. Thus, in a first phase the first unit stores in its n rows the bits of as many words arriving over the incoming channel branches and, simultaneously, reads out to the outgoing channel branches the bits of n words previously receiving from the terminal; at the same time the second unit stores in its m columns the bits of n successive words coming from the terminal and reads out to the terminal the bits of as many words previously fed in by the channels. In a second phase the roles of the two units are reversed.

Abstract translation: PCM / TDM终端具有m个并行接收线和m个并行发送线，用于n个字的复现序列，每个m个位，每个m个位，通过两个交替操作的转换单元发起或发往可连接到该终端的n个通道。 每个转换单元包括用于各个位的m.n个寄存器级的正交矩阵，分成m列和n行，第一单元与通道通信，而第二单元与终端通信，反之亦然。 在交替相位的交替阶段，其持续时间等于通过任何通道串行到达或离开的m位字所占据的时间段，与信道通信的单元具有其n行输入，并且其n行输出分别连接到输入和输出 信道分支，而与终端通信的单元具有其m列输入，并且其m列输出分别连接到发送和接收终端线路。 因此，在第一阶段中，第一单元在其n行存储通过输入信道到达的多个字的位分支，并同时读出输出信道，分支从终端先前接收的n个字的位; 同时，第二单元在其m列中存储来自终端的n个连续字的位，并且向终端读出先前由信道馈送的多个字的位。 在第二阶段，两个单位的角色相反。

公开(公告)号：AT360595B

公开(公告)日：1981-01-26

申请号：AT516476

申请日：1976-07-14

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： FROLA GIOVANNI ,  PERUCCA GIOVANNI

IPC: H04M17/02

公开(公告)号：IT1027384B

公开(公告)日：1978-11-20

申请号：IT6718775

申请日：1975-01-28

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： PERUCCA GIOVANNI ,  GIANCARLO GUASCHINO ,  BELFORTE P

IPC: H04Q11/04 ,  H04N

Abstract: A processor in a telephone exchange, monitoring the activity of r subscriber lines having each an incoming and an outgoing channel allocated to them, emits during respective halves of any 8-bit time slot in a 32-time-slot frame a pair of m-bit addresses x, y for each subscriber initiating or engaged in a conversation, these addresses respectively identifying an outgoing channel of a first (e.g. calling) subscriber and an incoming channel of a second (e.g. called) subscriber to be placed once per frame in communication with each other by a PCM switching network. The addresses of incoming and outgoing channels issuing from the processor during each time slot are separated in a distributor, the addresses y being inscribed in stages of a storage network respectively assigned to the 32.32.n channels identified by addresses x. The storage network consists of n random-access memories, one for each of n channel groups, divided into 32 sections of 32 stages each for as many 32-channel families. Each of 32 scanning intervals composed of n phases, occurring within a time slot, is reserved for the successive readout of homothetic stages in a respective set of n corresponding sections of all the memories, the set being divided into two subsets respectively scanned in the presence of relatively staggered enabling pulses also spanning n phases each whereby the readout of each subset starts after the beginning and terminates before the end of the corresponding enabling pulse.

公开(公告)号：DE2631899A1

公开(公告)日：1977-01-27

申请号：DE2631899

申请日：1976-07-15

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： FROLA GIOVANNI ,  PERUCCA GIOVANNI

IPC: H04M17/02 ,  H04M17/00

Abstract: The coin-operated public telephone, for local and long distance calls, has a coin channel which cooperates with a device connected to the armature of a first electromagnet and ensures that the coins enter serially. Another device detects whether the money already in the cash box and in the channel is sufficient to make the required call connection or to maintain such a connection. This device operates a state indicator. The first electromagnet armature operated devices that signal nd exchange. A third electromagnet shows the user when the telephone is out of order.

公开(公告)号：DE2538912A1

公开(公告)日：1976-03-25

申请号：DE2538912

申请日：1975-09-02

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BELFORTE PIERO ,  PERUCCA GIOVANNI

IPC: H04Q11/04

Abstract: A switching station for a telecommunication system, operating with pulse-code modulation, serves a multiplicity of incoming and outgoing PCM channels each consisting of a succession of 8-bit words cyclically interleaved with the words of 31 other channels in an assigned time slot of a 32-channel frame, 32 such frames being received and transmitted over as many signal paths forming a frame group. There are n incoming frame groups and n outgoing frame groups with synchronized bit phases in all the spatially separated channels thereof. A central processor controls the concurrent storage of all the incoming bits of a given phase in n pairs of 16-section input memories, each memory section consisting of 8 stages for the bits of a respective word from an incoming channel on a receiving signal path. During each time slot all the bits of each stored word are read out in parallel from the corresponding input-memory section into a similar section of an output memory from which they can be serially fed to a transmitting signal path during a period allocated to a selected outgoing channel. Thus, any incoming channel can communicate with any outgoing channel in the course of each frame.

公开(公告)号：DE2443526A1

公开(公告)日：1975-04-17

申请号：DE2443526

申请日：1974-09-11

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： MELINDO FLAVIO ,  PERUCCA GIOVANNI

IPC: H04Q11/04

Abstract: A PCM/TDM terminal has m parallel receiving lines and m parallel transmitting lines for recurrent sequences of n words, of m bits each, originating at or destined for n channels connectable to that terminal by way of two alternately operating conversion units. Each conversion unit comprises an orthogonal matrix of m.n register stages for individual bits, divided into m columns and n rows, the first unit communicating with the channels while the second unit communicates with the terminal and vice versa. In an alternation of switching phases whose duration equals the time period occupied by an m-bit word serially arriving or departing over any channel, the unit communicating with the channels has its n row inputs and its n row outputs respectively connected to the incoming and outgoing channel branches while the unit communicating with the terminal has its m column inputs and its m column outputs respectively connected to the transmitting and receiving terminal lines. Thus, in a first phase the first unit stores in its n rows the bits of as many words arriving over the incoming channel branches and, simultaneously, reads out to the outgoing channel branches the bits of n words previously receiving from the terminal; at the same time the second unit stores in its m columns the bits of n successive words coming from the terminal and reads out to the terminal the bits of as many words previously fed in by the channels. In a second phase the roles of the two units are reversed.

公开(公告)号：CH600713A5

公开(公告)日：1978-06-30

申请号：CH933076

申请日：1976-07-21

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： FROLA GIOVANNI ,  PERUCCA GIOVANNI

IPC: H04M17/02

公开(公告)号：DE2559058A1

公开(公告)日：1976-07-29

申请号：DE2559058

申请日：1975-12-30

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BELFORTE PIERO ,  GUASCHINO GIANCARLO ,  PERUCCA GIOVANNI

IPC: H04Q11/04

Abstract: A processor in a telephone exchange, monitoring the activity of r subscriber lines having each an incoming and an outgoing channel allocated to them, emits during respective halves of any 8-bit time slot in a 32-time-slot frame a pair of m-bit addresses x, y for each subscriber initiating or engaged in a conversation, these addresses respectively identifying an outgoing channel of a first (e.g. calling) subscriber and an incoming channel of a second (e.g. called) subscriber to be placed once per frame in communication with each other by a PCM switching network. The addresses of incoming and outgoing channels issuing from the processor during each time slot are separated in a distributor, the addresses y being inscribed in stages of a storage network respectively assigned to the 32.32.n channels identified by addresses x. The storage network consists of n random-access memories, one for each of n channel groups, divided into 32 sections of 32 stages each for as many 32-channel families. Each of 32 scanning intervals composed of n phases, occurring within a time slot, is reserved for the successive readout of homothetic stages in a respective set of n corresponding sections of all the memories, the set being divided into two subsets respectively scanned in the presence of relatively staggered enabling pulses also spanning n phases each whereby the readout of each subset starts after the beginning and terminates before the end of the corresponding enabling pulse.

公开(公告)号：ATA516476A

公开(公告)日：1980-06-15

申请号：AT516476

申请日：1976-07-14

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： FROLA GIOVANNI ,  PERUCCA GIOVANNI

IPC: H04M17/02

公开(公告)号：DE2626838A1

公开(公告)日：1976-12-23

申请号：DE2626838

申请日：1976-06-15

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： VINCENTIIS GIROLAMO DE ,  MELINDO FLAVIO ,  PERUCCA GIOVANNI

IPC: G06F11/16 ,  G06F11/20 ,  H04Q3/545 ,  G06F11/00 ,  G06F3/04 ,  G06F15/16 ,  H04Q1/20 ,  H04Q3/54

Abstract: Two processors UP1 and UP2, designed to test the operation of a pair of switching networks IN1 and IN2 in a telecommunication system through respective sets of peripheral interface units P11 etc. and P21 etc., are interconnected for parallel operation and are each linked with both sets of peripheral units via branched output and input multiples carrying outgoing and incoming messages. Each set of peripheral units is served by a respective bus bar BUS1, BUS2 connectable at one end, via an outgoing multiplexer MX12, MX22, to one of the branches of either output multiple 2, 3 and at the other end, via an incoming multiplexer MX11, MX21, to one of the branches of either input multiple 12, 13. The outgoing messages are also delivered, in parallel, to a pair of decision networks LS1, LS2 controlling the associated multiplexers MX12, MX22 in response to switching criteria obtained from a pair of intercommunicating synchronization circuits SN1, SN2 which are inserted in the two outgoing multiples upstream of their branching points. The sending of incoming messages from the peripheral units to the processors is preceded by access requests temporarily stored in parallel, under the control of a timing circuit BT, in a pair of buffer registers MT1 and MT2 respectively assigned to processors UP1 and UP2.