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    LOW STRESS VIAS
    32.
    发明申请
    LOW STRESS VIAS 有权
    低应力VIAS

    公开(公告)号：US20130026645A1

    公开(公告)日：2013-01-31

    申请号：US13193814

    申请日：2011-07-29

    Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS
    33.
    发明申请
    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS 有权
    多元化过程中的单次接触

    公开(公告)号：US20120326313A1

    公开(公告)日：2012-12-27

    申请号：US13170095

    申请日：2011-06-27

    Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    IPC: H01L23/52 ,  H01L21/768

    CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

    Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

    Device providing electrical contact to the surface of a semiconductor workpiece during processing
    34.
    发明授权
    Device providing electrical contact to the surface of a semiconductor workpiece during processing 失效

    公开(公告)号：US07282124B2

    公开(公告)日：2007-10-16

    申请号：US10459320

    申请日：2003-06-10

    Applicant: Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

    Inventor： Homayoun Talieh ,  Cyprian Uzoh ,  Bulent M. Basol

    IPC: C25D17/00

    CPC classification number: B23H3/04 ,  B23H5/08 ,  C25D5/08 ,  C25D17/00 ,  C25D17/001 ,  C25D17/005 ,  C25F7/00 ,  H01L21/2885

    Abstract: Substantially uniform deposition of conductive material on a surface of a substrate, which substrate includes a semiconductor wafer, from an electrolyte containing the conductive material can be provided by way of a particular device which includes first and second conductive elements. The first conductive element can have multiple electrical contacts, of identical or different configurations, or may be in the form of a conductive pad, and can contact or otherwise electrically interconnect with the substrate surface over substantially all of the substrate surface. Upon application of a potential between the first and second conductive elements while the electrolyte makes physical contact with the substrate surface and the second conductive element, the conductive material is deposited on the substrate surface. It is possible to reverse the polarity of the voltage applied between the anode and the cathode so that electro-etching of deposited conductive material can be performed.

    Method and apparatus for processing a substrate with minimal edge exclusion
    35.
    发明授权
    Method and apparatus for processing a substrate with minimal edge exclusion 有权
    用于处理具有最小边缘排除的基板的方法和装置

    公开(公告)号：US06942780B2

    公开(公告)日：2005-09-13

    申请号：US10460032

    申请日：2003-06-11

    Applicant: Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

    Inventor： Bulent M. Basol ,  Cyprian Uzoh ,  Homayoun Talieh

    IPC: C25D7/12 ,  C25D17/00 ,  C25D17/08 ,  C25D21/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768 ,  C25D5/00 ,  C25D5/08 ,  C25F3/00

    CPC classification number: C25D5/02 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/76877

    Abstract: An apparatus for processing a material on a wafer surface includes a cavity defined by a peripheral wall and configured to direct a process solution and direct it to the surface to to a first wafer surface region without being directed to a second wafer surface region, a head configured to hold the wafer so that the surface of the wafer faces the cavity, and an electrical contact member positioned outside the cavity peripheral wall and configured to contact the second wafer surface region extending beyond the cavity, when the wafer is moved relative to the contact member. Advantages of the invention include substantially full surface treatment of the wafer.

    Abstract translation: 用于处理晶片表面上的材料的设备包括由周壁限定的空腔，并且被配置为引导处理溶液并将其引导到表面到达第一晶片表面区域而不被引导到第二晶片表面区域，头部 被配置为保持所述晶片使得所述晶片的表面面向所述空腔;以及电接触构件，其定位在所述腔周壁外部并且被配置为当所述晶片相对于所述触点移动时接触延伸超过所述腔的所述第二晶片表面区域 会员。 本发明的优点包括晶片的基本全表面处理。

    Anode assembly for plating and planarizing a conductive layer
    36.
    发明授权
    Anode assembly for plating and planarizing a conductive layer 有权
    用于电镀和平坦化导电层的阳极组件

    公开(公告)号：US06478936B1

    公开(公告)日：2002-11-12

    申请号：US09568584

    申请日：2000-05-11

    Applicant: Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

    Inventor： Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

    IPC: C25B1103

    CPC classification number: C25D17/14 ,  C25F7/00

    Abstract: A particular anode assembly can be used to supply a solution for any of a plating operation, a planarization operation, and a plating and planarization operation to be performed on a semiconductor wafer. The anode assembly includes a rotatable shaft disposed within a chamber in which the operation is performed, an anode housing connected to the shaft, and a porous pad support plate attached to the anode housing. The support plate has a top surface adapted to support a pad which is to face the wafer, and, together with the anode housing, defines an anode cavity. A consumable anode may be provided in the anode cavity to provide plating material to the solution. A solution delivery structure by which the solution can be delivered to said anode cavity is also provided. The solution delivery structure may be contained within the chamber in which the operation is performed. A shield can also be mounted between the shaft and an associated spindle to prevent leakage of the solution from the chamber.

    Abstract translation: 可以使用特定的阳极组件来提供用于在半导体晶片上进行的电镀操作，平面化操作和电镀和平面化操作中的任何一种的解决方案。 阳极组件包括设置在其中执行操作的室内的可旋转轴，连接到轴的阳极壳体和附接到阳极壳体的多孔垫支撑板。 支撑板具有适于支撑面向晶片的焊盘的顶表面，并且与阳极壳体一起限定阳极腔。 可以在阳极腔中设置消耗性阳极以向溶液提供电镀材料。 还提供了可以将溶液输送到所述阳极腔的溶液输送结构。 溶液输送结构可以包含在进行操作的室内。 护罩还可以安装在轴和相关主轴之间，以防止溶液从腔室泄漏。

    Low stress vias
    37.
    发明授权
    Low stress vias 有权
    低压通孔

    公开(公告)号：US08816505B2

    公开(公告)日：2014-08-26

    申请号：US13193814

    申请日：2011-07-29

    Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    Systems and methods for producing flat surfaces in interconnect structures
    39.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权
    用于在互连结构中产生平坦表面的系统和方法

    公开(公告)号：US08728934B2

    公开(公告)日：2014-05-20

    申请号：US13168839

    申请日：2011-06-24

    Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    IPC: H01L21/4763

    CPC classification number: H01L21/76898 ,  H01L21/3212 ,  H01L21/32125 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/7688 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

    Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。 一个特征是形成互连结构的方法，其导致互连结构具有共面或平坦的顶表面。 另一个特征是形成互连结构的方法，其导致互连结构具有相对于衬底顶表面向上倾斜大于零的表面。 互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

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