公开(公告)号：JP2012038389A

公开(公告)日：2012-02-23

申请号：JP2010178780

申请日：2010-08-09

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： FURUYA KIYOHIRO ,  MATSUI YOSHINORI

IPC: G11C11/4074 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07

CPC classification number: G11C11/4074 ,  G11C5/147

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device including an internal circuit operating at constant voltage not depending on power source voltage supplied from outside and an internal circuit operating at the power source voltage, which suppresses the occurrence of malfunction caused due to large variation in power source voltage supplied from outside.SOLUTION: A semiconductor device comprises an internal circuit and an internal voltage generating circuit for generating an internal voltage stabilized with respect to variation in power source voltage supplied from outside and for supplying the internal voltage to the internal circuit. The internal voltage generating circuit stops the stabilization operation with respect to the internal voltage when the power source voltage has increased over a predetermined value, and controls the internal voltage to increase along with the increase in power source voltage.

Abstract translation: 要解决的问题：提供一种半导体器件，其包括不依赖于从外部提供的电源电压的恒定电压工作的内部电路和在电源电压下工作的内部电路，从而抑制由于 从外部供电的电源电压变化很大。 解决方案：半导体器件包括内部电路和内部电压产生电路，用于产生相对于从外部提供的电源电压的变化而稳定的内部电压并且用于将内部电压提供给内部电路。 当电源电压增加超过预定值时，内部电压产生电路停止相对于内部电压的稳定操作，并且随着电源电压的增加而控制内部电压增加。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2009237980A

公开(公告)日：2009-10-15

申请号：JP2008084260

申请日：2008-03-27

Applicant: Elpida Memory Inc ,  Hitachi Ltd ,  エルピーダメモリ株式会社 ,  株式会社日立製作所

Inventor： MIURA SEISHI ,  MATSUI YOSHINORI ,  ABE KAZUHIKO ,  KANEKO SHOJI

IPC: G06F12/00

CPC classification number: G11C7/1075 ,  G06F13/1663

Abstract: PROBLEM TO BE SOLVED: To provide a multiport memory that increases the speed of data communication between a plurality of information processing devices, and also to provide an information processing system that is fast and easy to use. SOLUTION: In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by certain ports and memory areas shared by a plurality of ports. In this occasion, immediately after the occurrence of a request from each port, the status of this request may be outputted from other ports. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种提高多个信息处理装置之间的数据通信速度的多端口存储器，并且还提供快速且易于使用的信息处理系统。 解决方案：在信息处理系统中，多个信息处理设备CHIP0和CHIP1连接到具有多个端口的多端口存储器MPMEM0，并且多端口存储器MPMEM0中的存储区域可以改变为某些端口占用的存储区域 以及由多个端口共享的存储区域。 在这种情况下，在每个端口发出请求之后，可以从其他端口输出该请求的状态。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009170002A

公开(公告)日：2009-07-30

申请号：JP2008004304

申请日：2008-01-11

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C11/401 ,  G11C11/407

CPC classification number: G11C7/1075

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a plurality of ports, which reduces a clock cycle required for data transfer between a common memory cell array and an exclusive memory cell array. SOLUTION: A DualPortDRAM 70 is provided with internal address generating circuits 726, 727, 728 and control circuits 729, 730. The internal address generating circuits 726 and 727 generate an address of transfer source or transfer destination in data transfer. Also, the control circuit 729 causes the internal address generating circuit 727 to generate an address of transfer source based on a data transfer command, while causing the internal address generating circuit 726 to generate an address of transfer destination, and inputs successively data output by burst-read from a memory cell array 716 as a transfer source to a memory cell array 705 as a transfer destination through an internal data bus. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种设置有多个端口的半导体存储器件，其减小了在公共存储器单元阵列和专用存储器单元阵列之间的数据传输所需的时钟周期。 解决方案：DualPortDRAM 70具有内部地址产生电路726,727,728和控制电路729,730。内部地址产生电路726和727在数据传输中产生传送源或传送目的地的地址。 此外，控制电路729使内部地址生成电路727基于数据传送命令生成传送源的地址，同时使内部地址生成电路726生成传送目的地的地址，并连续地输入由突发输出的数据 从作为转移源的存储单元阵列716读取作为通过内部数据总线的转移目的地的存储单元阵列705。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2009009633A

公开(公告)日：2009-01-15

申请号：JP2007168947

申请日：2007-06-27

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： TOHO YOSHIROU ,  OISHI HAYATO ,  HARAGUCHI YOSHINORI ,  MATSUI YOSHINORI

IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

CPC classification number: G11C5/025 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device which increases access speed and reduces a wiring area for an IO bus in the center of the chip by equalizing a distance between each memory cell and DQ pads to reduce variation in access time. SOLUTION: The semiconductor storage device has a memory cell array composed of blocks divided into a plurality of data IO pads, and the memory cell array is divided into a plurality of banks. The bank has a plurality of divided memory cell areas, the block formed by the memory cell area for each bank, and a preset number of data IO pads prepared correspondingly to the memory cell in the block. The IO pads are arranged in the vicinity of the corresponding block. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种半导体存储装置，其通过均衡每个存储单元和DQ垫之间的距离来增加存取速度并减少用于芯片中心的IO总线的布线面积，以减少存取时间的变化 。 解决方案：半导体存储装置具有由划分成多个数据IO焊盘的块组成的存储单元阵列，并且存储单元阵列被分成多个存储体。 存储体具有多个划分的存储单元区域，由每个存储体的存储单元区域形成的块以及对应于该块中的存储单元的预定数量的数据IO块。 IO垫布置在相应块的附近。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2005222593A

公开(公告)日：2005-08-18

申请号：JP2004028272

申请日：2004-02-04

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G11C7/00 ,  G11C11/403 ,  G11C11/406

CPC classification number: G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory in which refreshing of rational, highly reliable and low power consumption can be performed in line with a retention time of a memory cell, and a refreshing method of the semiconductor memory.
SOLUTION: When the semiconductor memory is entered to a refresh-mode, a retention time of a memory cell is measured for each word line, a plurality of refresh-periods corresponding to the retention time of the memory cell are set, and the memory cell is refreshed according to the plurality of refresh-periods.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 解决的问题：提供一种半导体存储器，其中可以根据存储单元的保持时间进行合理，高度可靠和低功耗的刷新，以及半导体存储器的刷新方法。 解决方案：当半导体存储器进入刷新模式时，对每个字线测量存储单元的保持时间，设置与存储单元的保持时间对应的多个刷新周期，以及 根据多个刷新周期刷新存储器单元。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004139552A

公开(公告)日：2004-05-13

申请号：JP2003175431

申请日：2003-06-19

Applicant: Elpida Memory Inc ,  エルピーダメモリ株式会社

Inventor： MATSUI YOSHINORI

IPC: G06F1/18 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4093

CPC classification number: G11C7/1048 ,  G06F13/4243 ,  G06F13/4256 ,  G11C7/10 ,  G11C8/18 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/028 ,  G11C29/50012

Abstract: PROBLEM TO BE SOLVED: To provide a memory system capable of realizing high-speed operation by reducing influence or the like by a reflection signal by branch and impedance mismatching of various kinds of wiring between a memory controller and a memory module, and influence or the like by transmission delay of data, command addresses or clock signals in the memory module. SOLUTION: This memory system is provided with the memory controller, and the memory module with DRAMs mounted. The memory system is so structured that a buffer is mounted on the memory module, and the buffer is connected to the memory controller through data wiring, command address wiring and clock wiring; and the DRAMs on the memory module are connected to the buffer through internal data wiring, internal command address wiring and internal clock wiring. The data wiring, the command address wiring and the clock wiring may be cascaded with a buffer of another memory module. High-speed data transmission is carried out between the DRAMs on the memory module and the buffer by using a data phase signal synchronized with the clock signal. COPYRIGHT: (C)2004,JPO