公开(公告)号：JPS6157146A

公开(公告)日：1986-03-24

申请号：JP17966184

申请日：1984-08-29

Applicant: Fujitsu Ltd

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI ,  INOUE YUKINORI ,  NAKAHARA YASUHIRO ,  NEGISHI HITOSHI ,  NAKAMURA OSAMU

Abstract: PURPOSE: To improve the utilizing efficiency of a time slot by setting a communication bus identification number to each communication controller, adding it to a control section in a time slot and transmitting the result.
CONSTITUTION: A transmission data generated by a data terminal device 74 is stored in a transmission buffer register circuit 72 via a level converting circuit 73, and when a prescribed amount of data is stored, a control section 70 detects an idle time slot. The control section 70 detecting the idle time slot writes a communication bus identification number and a USE bit and transmits a transmission data via a data transmission line 52. the time slot assigned to the own device reaches the communication controller at the reception side and it is coincident with the assigned communication bus identification number, the data of the time slot is written in a reception buffer register 71 to reset the USE bit and the data is transmitted to the terminal device 74.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过将通信总线识别号码设置给每个通信控制器来提高时隙的利用效率，将其添加到时隙中的控制部分并发送结果。 构成：由数据终端装置74生成的发送数据通过电平转换电路73存储在发送缓冲寄存器电路72中，并且当存储规定量的数据时，控制部70检测空闲时隙。 检测空闲时隙的控制部70写入通信总线识别号和USE位，并经由数据传输线52发送发送数据。分配给自身装置的时隙到达接收侧的通信控制器， 与分配的通信总线识别号一致，时隙的数据被写入接收缓冲器寄存器71以复位USE位，并且数据被发送到终端装置74。

公开(公告)号：JPS60170352A

公开(公告)日：1985-09-03

申请号：JP2537584

申请日：1984-02-14

Applicant: FUJITSU LTD

Inventor： MITA TERUYOSHI ,  SUZUKI YOUICHI ,  NAKAMURA OSAMU

IPC: H04L7/00 ,  H04L12/42

Abstract: PURPOSE:To eliminate the necessity of a high-grade phase regulating circuit so as to suppress the increase in the cost of a communication device, by installing a phase regulating circuit to each of plural communication devices commonly using an annular main line. CONSTITUTION:A phase regulating circuit 23 is provided in a communication device 21 and has a converting or invertedly converting phase regulating function. Another phase regulating circuit 24 is provided in another communication device 22 and has the same function as the regulating circuit 23 has. Then the regulating circuit 23 of the communication device 21 is set to a condition where phase regulation is inhibited, and the regulating circuit 24 of the communication device 22 is set to another circuit where phase regulation is controlled. Since the phase regulating function of the regulating circuit 23 is inhibited, a stable element timing signal can be supplied to a synchronizing MODEM5. Therefore, the necessity of a high-grade phase regulating circuit is eliminated and, as a result, the cost of the communication device can be prevented from increasing.

公开(公告)号：JPS59231950A

公开(公告)日：1984-12-26

申请号：JP10712483

申请日：1983-06-15

Applicant: FUJITSU LTD

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI ,  KITANO YOSHIHIRO ,  NAKAHARA YASUHIRO ,  NEGISHI TSUTAE

IPC: H04L5/22 ,  H04L12/12 ,  H04L11/00 ,  H04J3/00

Abstract: PURPOSE:To eliminate the malfunction of a terminal device without proving a reception data buffer more than the required number of sets to a line correspondence section by eliminating a time slot remaining to a transmission line after the line correspondence section releases the time slot. CONSTITUTION:The line correspondence section 12 is provided corresponding to a common control section of a station node of a data highway and the correspondence section 12 is provided with a transmission buffer 20, a reception buffer 22, a register 24 and an address comparator 25. Further, an S/P converter 21, a P/S converter 23 and a timer 26 or the like are provided. When communication is finished by the correspondence section 12, a program is read by the OFF of a signal 31 for a line cut-off request from the terminal device so as to activate the buffer 22 and the converter 23. After the correspondence section 12 opens the time slot, the time slot remaining to the transmission line by the register 24, the address comparator 25 and the timer 26 or the like is eliminated, the number of the buffers 22 required for the correspondence section 12 is reudced, thereby preventing the malfunction of the terminal device.

公开(公告)号：JPS59221137A

公开(公告)日：1984-12-12

申请号：JP9619383

申请日：1983-05-31

Applicant: FUJITSU LTD

Inventor： MITA TERUYOSHI ,  TAKEYAMA AKIRA

IPC: H04L29/06 ,  H04L12/00 ,  H04L13/00 ,  H04L11/00

Abstract: PURPOSE:To improve the utilizing efficiency in a communication system by transferring and renewing an attribute of a caller side to an incoming side to eliminate the necessity of notifying the attribute of a line corresponding section in the communication with an opposite party having different attributes thereby attaining the connection to a line having a broad range of attribute. CONSTITUTION:The setting of the attribute of the line corresponding section 2-n accommodating a terminal device 6 is renewed from a common section, an attribute equivalent to the attribute set in the line corresponding section (incoming side) accommodating a computer system, for example, at the request of exchange connection is transferred to the caller side to control an attribute storage device at the caller side as if it were renewed. A circuit block CMD decodes Dial to attain exchange connection and also renew contents of a storage device MEM of the line corresponding section. Further, a clock signal geneating circuit I/N connected to a synchronizing circuit SY generates a clock signal having a fundamental period at each communication speed. Then a clock signal generating circuit I/N connected to a synchronizing circuit SY generates the clock signal of the fundamental period at each communication speed. A selecting circuit SEL selects one of the said clock signals depending on the content of the device MEM to match the communication speed between a data communication terminal and the line corresponding section. Data from the line corresponding section is inserted to a time division multiplex transmission line by a block DI.

公开(公告)号：JPS5997257A

公开(公告)日：1984-06-05

申请号：JP20696782

申请日：1982-11-26

Applicant: FUJITSU LTD

Inventor： NAKAHARA YASUHIRO ,  MITA TERUYOSHI

IPC: H04L25/02 ,  H04L1/24

Abstract: PURPOSE:To attain automatically continuous diagnosis of all driver/receiver elements by providing a means encoding an output signal of plural driver elements and inputting reflectingly the signal to the receiver elements. CONSTITUTION:A connector 12 of a line corresponding section 6 and a connector 15 of a reflecting tester 21 are connected. A test pattern signal is transmitted from a program control section 3 to a driver circuit 10 of the line corresponding section 6, and an output of a receiver circuit 16 is inputted to an encoder 19 through a setting board 18. A signal converted at the encoder 19 is inputted to the receiver circuit 11 through a driver circuit 17, the connector 15 and the connector 12. The output of the receiver circuit 11 is checked finally by a program control section 3.

公开(公告)号：JPS5997249A

公开(公告)日：1984-06-05

申请号：JP20696582

申请日：1982-11-26

Applicant: FUJITSU LTD

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

IPC: H04L12/42

Abstract: PURPOSE:To attain easy detection of a dead packet by counting the number of packet transmission requests from a sub-system and determining the priority of the sub-system automatically. CONSTITUTION:A transmission data transmitted from the sub-system 24 is stored to a transmission buffer memory 21 via a packet exchange. A common control circuit 18 receiving the packet transmission request counts a counter of a packet transmission request signal count circuit 15 and detects a dead packet passing through a data buffer register 8. The decoded value of the circuit 15 and the priority of an incoming packet are compared by a comparator circuit 17. When the decoded value is larger than or equal to the priority of the packet, the use of the dead packet is possible and when smaller, the dead packet is not used.

公开(公告)号：JPS5991558A

公开(公告)日：1984-05-26

申请号：JP20238582

申请日：1982-11-18

Applicant: FUJITSU LTD

Inventor： MITA TERUYOSHI

IPC: G06F11/28 ,  G06F11/36

Abstract: PURPOSE:To generate a breakpoint interruption without increasing storage capacity by providing a data processor having a readable/writable storage device with a breakpoint interruption indicating means. CONSTITUTION:A microprocessor 3 is connected to an external register group 1, a parity generator 2-3 and a parity checking circuit 2-4. In the test mode, the Q output of an FF 1-1 and the Q output of an FF 1-2 are turned to ''1''. The same information as that read out from a specified area in a memory is read out from the microprocessor 3 and written in a memory 2-2. The parity checking circuit 2-4 turns an output line 2-10 to ''1'' to generate an interruption. Consequently, the Q output of an FF 1-3 is turned to ''1'' and the breakpoint interruption is detected. Thus, a program can be tested by a simple circuit.

公开(公告)号：JPS5958937A

公开(公告)日：1984-04-04

申请号：JP16892182

申请日：1982-09-28

Applicant: Fujitsu Ltd

Inventor： KITANO YOSHIHIRO ,  MITA TERUYOSHI

IPC: H04L12/42

CPC classification number: H04L12/42

Abstract: PURPOSE:To obtain a data highway system with high efficiency, by comparing the priority of a packet with that of a sub-system, and using the said idle packet when the priority of the said sub-system is larger or both the priorities are equal. CONSTITUTION:A data synchronism detecting circuit 11 detects the synchronizing flag of a frame header arriving at each prescribed period. When an arrival packet is in use and the addressed address and the address of a sub-system address set circuit 14 are compared at a comparison circuit 16, a common control circuit 18 writes the data content of the arrival packet to a receiving buffer memory 20. When a data is stored in the receiving buffer memory 20, the channel control circuit transmits the data to a sub-system 24 via a drive circuit 22. A response circuit 13 writes the receiving state to a response section in the packet with the indication of the common control circuit 18 and a channel control circuit 19.

Abstract translation: 目的：通过比较分组的优先级与子系统的优先级，并且当所述子系统的优先级较大或优先级相等时，使用所述空闲分组来获得高效率的数据公路系统 。 构成：数据同步检测电路11检测在每个规定的周期内到达的帧头的同步标志。 当使用到达分组并且比较电路16比较寻址地址和子系统地址设置电路14的地址时，公共控制电路18将到达分组的数据内容写入接收缓冲存储器20 当数据存储在接收缓冲存储器20中时，信道控制电路经由驱动电路22将数据发送到子系统24.响应电路13将接收状态写入分组中的响应部分，并具有指示 的公共控制电路18和通道控制电路19。

公开(公告)号：JPS595761A

公开(公告)日：1984-01-12

申请号：JP11443582

申请日：1982-06-30

Applicant: Fujitsu Ltd

Inventor： NAKAMURA OSAMU ,  MITA TERUYOSHI

IPC: H04L12/43

CPC classification number: H04L12/43

Abstract: PURPOSE:To making a data transfer speed constant and to eliminate the need for frame monitoring, by providing a means of transmitting data from a slave station to a master station synchronously with the significance/insignificance flag of data set when the data is sent from the master station to the slave station. CONSTITUTION:The station 3 of the master station 6 while writing transmit data to a slave station in the data area of a time slot M writes ''1'' in an AV area and then transmits the data to a loop transmission line 1. On the other hand, stations 4 and 5 including slave stations 7 and 8 check on AV areas of time slots from the master station and set the contents of the time slot with ''1'' as significant data in an LS including the slave station. At this time, when there is data to be sent from the slave station to the master station, the transmit data is written in the data area of a time slot S and the AV area with ''1'' is sent out to the transmission line 1 as it is. The master station checks on the AV area of the time slot after one round and when it indicates ''1'', the data from the slave station is set in the LS as significant data.

Abstract translation: 目的：为了使数据传输速度恒定并且消除对帧监视的需要，通过提供一种将数据从从站发送到主站同时与数据集的有效/无意义标志同步发送的方法 主站到从站。 构成：在将时隙M的数据区域中的从站发送数据的时候，主站6的站3在AV区域中写入“1”，然后将数据发送到环路传输线路1上 另一方面，包括从站7和8的站4和5检查来自主站的时隙的AV区域，并将包含从站的LS中的“1”的时隙的内容设置为有效数据。 此时，当从从站发送数据到主站时，将发送数据写入时隙S的数据区域，将具有“1”的AV区域发送到发送 第1行。 主站在一轮后检查时隙的AV区域，当它指示“1”时，来自从站的数据被设置在LS中作为重要数据。

公开(公告)号：JPS5856295B2

公开(公告)日：1983-12-14

申请号：JP1411879

申请日：1979-02-09

Applicant: Fujitsu Ltd

Inventor： SUZUKI YOICHI ,  MITA TERUYOSHI

IPC: H04L12/42

CPC classification number: H04L12/42