公开(公告)号：US20220376093A1

公开(公告)日：2022-11-24

申请号：US17324183

申请日：2021-05-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Richard F. Taylor, III ,  Mankyu Yang ,  Alexander L. Martin ,  Judson R. Holt ,  Jagar Singh

IPC: H01L29/735 ,  H01L21/84 ,  H01L29/739 ,  H01L29/66 ,  H01L27/12 ,  H01L29/10 ,  H01L29/08

Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.

公开(公告)号：US11462632B2

公开(公告)日：2022-10-04

申请号：US17130121

申请日：2020-12-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Ali Razavieh ,  Halting Wang

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

公开(公告)号：US11424349B1

公开(公告)日：2022-08-23

申请号：US17177490

申请日：2021-02-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/06

Abstract: A lateral bipolar junction transistor (BJT) device includes: an emitter region, a collector region, and a base region, the base region positioned between and laterally separating the emitter region and the collector region, the base region including an intrinsic base region; and a cavity formed in a semiconductor substrate and filled with an insulating material, the cavity physically separating a lower surface of the intrinsic base region from the semiconductor substrate.

公开(公告)号：US11990535B2

公开(公告)日：2024-05-21

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/02532 ,  H01L21/2251 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11908898B2

公开(公告)日：2024-02-20

申请号：US17456943

申请日：2021-11-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu ,  Alexander M. Derrickson

IPC: H01L29/10 ,  H01L29/735 ,  H01L29/66

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

公开(公告)号：US11855197B2

公开(公告)日：2023-12-26

申请号：US17580127

申请日：2022-01-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Alexander M. Derrickson ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

公开(公告)号：US11837460B2

公开(公告)日：2023-12-05

申请号：US17550835

申请日：2021-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alexander Martin

IPC: H01L29/735 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region composed of semiconductor material; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and an extrinsic base contact wrapping around the semiconductor material of the extrinsic base region.

公开(公告)号：US11799021B2

公开(公告)日：2023-10-24

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.

公开(公告)号：US20230275083A1

公开(公告)日：2023-08-31

申请号：US17807899

申请日：2022-06-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson

IPC: H01L27/06 ,  H01L29/735 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8249 ,  H01L29/66

CPC classification number: H01L27/0623 ,  H01L29/735 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/8249 ,  H01L29/6625 ,  H01L29/66742 ,  H01L29/66439

Abstract: Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).

公开(公告)号：US11646361B2

公开(公告)日：2023-05-09

申请号：US17191886

申请日：2021-03-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Alexander M. Derrickson ,  Haiting Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/7851

Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.