公开(公告)号：US12278269B2

公开(公告)日：2025-04-15

申请号：US17852966

申请日：2022-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. Raghunathan ,  Vibhor Jain ,  Qizhi Liu ,  Yves T. Ngu ,  Ajay Raman ,  Rajendran Krishnasamy ,  Alvin J. Joseph

IPC: H01L29/10 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

公开(公告)号：US12243935B2

公开(公告)日：2025-03-04

申请号：US18487114

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US12176427B2

公开(公告)日：2024-12-24

申请号：US17931938

申请日：2022-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

公开(公告)号：US12009412B2

公开(公告)日：2024-06-11

申请号：US17549013

申请日：2021-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/732 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

公开(公告)号：US11990535B2

公开(公告)日：2024-05-21

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L21/02532 ,  H01L21/2251 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/165 ,  H01L29/66242

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US11923446B2

公开(公告)日：2024-03-05

申请号：US17503345

申请日：2021-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/435 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66431

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240045156A1

公开(公告)日：2024-02-08

申请号：US17816790

申请日：2022-08-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Vibhor Jain ,  Steven M. Shank

IPC: G02B6/42

CPC classification number: G02B6/4212 ,  G02B6/4215 ,  G02B6/4295 ,  G02B6/4274

Abstract: A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.

公开(公告)号：US11855197B2

公开(公告)日：2023-12-26

申请号：US17580127

申请日：2022-01-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Alexander M. Derrickson ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

公开(公告)号：US11804541B2

公开(公告)日：2023-10-31

申请号：US17578011

申请日：2022-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with an emitter/collector (E/C) contact to a doped semiconductor well and related methods. A bipolar transistor structure according to the disclosure may include a doped semiconductor well over a semiconductor substrate. An insulative region is on the doped semiconductor well. A base layer is on the insulative region, and an emitter/collector (E/C) layer on the insulative region and adjacent a first sidewall of the base layer. An E/C contact to the doped semiconductor well includes a lower portion adjacent the insulative region and an upper portion adjacent and electrically coupled to the E/C layer.

公开(公告)号：US11799021B2

公开(公告)日：2023-10-24

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.