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    PHOTODETECTOR ARRAY WITH DIFFRACTION GRATINGS HAVING DIFFERENT PITCHES
    31.
    发明申请
    PHOTODETECTOR ARRAY WITH DIFFRACTION GRATINGS HAVING DIFFERENT PITCHES 有权

    公开(公告)号：US20220155535A1

    公开(公告)日：2022-05-19

    申请号：US17099834

    申请日：2020-11-17

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Yusheng Bian ,  Siva P. Adusumilli ,  Mark D. Levy

    IPC: G02B6/42 ,  H01L31/0256 ,  H01L31/02

    Abstract: A photodetector array includes a substrate, and an array of pixels over the substrate. Each pixel includes a set of diffraction gratings directly on a semiconductor photodetector. A pitch of the set of diffraction gratings associated with each pixel in the array of pixels are different to enable each pixel to detect a specific wavelength of light different than other pixels of the array of pixels. An air cavity may be provided in the substrate under the germanium photodetector to improve light absorption. A method of forming the photodetector array is also disclosed.

    Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method
    33.
    发明授权
    Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method 有权

    公开(公告)号：US11152394B1

    公开(公告)日：2021-10-19

    申请号：US16992445

    申请日：2020-08-13

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Mark D. Levy ,  Siva P. Adusumilli

    IPC: H01L27/12 ,  H01L21/84 ,  H01L21/763

    Abstract: A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. The structure also includes a first active device and a second active device. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region is in the semiconductor substrate under the buried insulator layer. The polycrystalline isolation region is under the first active device, but not under the second active device. The polycrystalline isolation region extends to different depths into the semiconductor substrate. The first and second active devices may include monocrystalline active regions, and a third polycrystalline active region may also be in the SOI layer over the polycrystalline isolation region.

    Semiconductor structure including photodiode-based fluid sensor and methods
    35.
    发明授权
    Semiconductor structure including photodiode-based fluid sensor and methods 有权

    公开(公告)号：US12281996B2

    公开(公告)日：2025-04-22

    申请号：US17808176

    申请日：2022-06-22

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

    IPC: G01N27/06 ,  H10F30/223 ,  H10F71/00 ,  H10F77/14

    Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

    Field effect transistor
    39.
    发明授权
    Field effect transistor 有权

    公开(公告)号：US12142686B2

    公开(公告)日：2024-11-12

    申请号：US17330780

    申请日：2021-05-26

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anthony K. Stamper ,  Uzma Rana ,  Steven M. Shank ,  Mark D. Levy

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

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