公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC: H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

公开(公告)号：US20240063219A1

公开(公告)日：2024-02-22

申请号：US17819980

申请日：2022-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Jerry Joseph James ,  Steven J. Bentley ,  Francois Hebert ,  Richard J. Rassel

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/0607

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.

公开(公告)号：US12143112B2

公开(公告)日：2024-11-12

申请号：US18045909

申请日：2022-10-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma

IPC: H03K5/04 ,  H03K17/687

Abstract: Disclosed are circuits for controlling slew rate of a transistor during switching. Each circuit includes a first transistor (e.g., a gallium nitride (GaN)-based high electron mobility transistor (HEMT) or metal-insulator-semiconductor HEMT (MISHEMT)), a capacitor, and a second transistor. The first transistor includes a first gate connected to a pad for receiving a pulse-width modulation (PWM) signal, a first drain region connected to a first plate of the capacitor, and a first source region. The second transistor includes a second gate connected to a second plate of the capacitor, a second drain region, and a second source region and is connected to both the pad and the first transistor. The connection between the first and second transistors varies depending on whether the first transistor is an enhancement or depletion mode device and on whether the slew rate control is employed for on state or off state switching.

公开(公告)号：US20240204764A1

公开(公告)日：2024-06-20

申请号：US18065768

申请日：2022-12-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy

IPC: H03K17/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H03K17/08 ,  H01L29/404 ,  H01L29/7816

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：US20240063301A1

公开(公告)日：2024-02-22

申请号：US17891244

申请日：2022-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma

IPC: H01L29/778 ,  H01L29/20 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L27/0266 ,  H01L29/0657

Abstract: Disclosed are protective structures using depletion-mode and enhancement-mode transistors. A structure according to the disclosure may include a depletion-mode transistor having a gate coupled to ground and a first source/drain terminal. An enhancement-mode transistor includes a gate coupled to a second source/drain terminal of the depletion-mode transistor and a first source/drain terminal coupled to the gate of the depletion-mode transistor. The depletion-mode transistor limits a current flow from the first source/drain terminal to the gate of the enhancement-mode transistor.

公开(公告)号：US20250142860A1

公开(公告)日：2025-05-01

申请号：US18385255

申请日：2023-10-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Santosh Sharma ,  Johnatan A. Kantarovsky ,  Mark D. Levy ,  Michael J. Zierak

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.

公开(公告)号：US20250120155A1

公开(公告)日：2025-04-10

申请号：US18376668

申请日：2023-10-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Johnatan A. Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Steven J. Bentley

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.

公开(公告)号：US20250089284A1

公开(公告)日：2025-03-13

申请号：US18243910

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Mark D. Levy ,  Steven J. Bentley

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

Abstract: A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.

公开(公告)号：US20250070781A1

公开(公告)日：2025-02-27

申请号：US18455669

申请日：2023-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Mei Yu Soh

IPC: H03K19/003 ,  H03K17/0412

Abstract: Disclosed circuit structure embodiments include an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistors when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). In some embodiments, the slew rate controller includes: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.

公开(公告)号：US20240234533A1

公开(公告)日：2024-07-11

申请号：US18152710

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.