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    MULTIPROCESSOR SYSTEM
    32.
    发明专利
    MULTIPROCESSOR SYSTEM 失效

    公开(公告)号：JPH04195664A

    公开(公告)日：1992-07-15

    申请号：JP33155790

    申请日：1990-11-28

    Applicant: HITACHI LTD

    Inventor： KUROSAWA KENICHI ,  SAITO MASAHIKO ,  KOBAYASHI YOSHIKI

    IPC: G06F15/16 ,  G06F9/52 ,  G06F15/177

    Abstract: PURPOSE:To synchronize plural processors by using a small number of instructions by enabling synchronizing facilities to control the synchronism of their processor element while grasping the state of other synchronizing facilities through a bus arbitrating circuit. CONSTITUTION:A synchronism control means that the synchronizing facilities have grasp the execution state of a register transfer instruction on other synchronizing facilities A4 through the bus arbitrating circuit A5 and during the execution of the register transfer instruction, register transfer is carried out through a communication bus if transfer-destination synchronizing facilities are executing a corresponding register transfer instruction. When the opposite synchronizing facilities are not executing the corresponding register transfer instruction, this processor element A1 is stopped temporarily until the opposite synchronizing facilities execute the corresponding register transfer instruction to obtain synchronism with the transfer-destination processor element. Consequently, the processor elements can be synchronized by using a small number of instructions.

    DEVICE AND METHOD FOR PARALLEL PROCESSING
    34.
    发明专利
    DEVICE AND METHOD FOR PARALLEL PROCESSING 失效

    公开(公告)号：JPH03129433A

    公开(公告)日：1991-06-03

    申请号：JP17742590

    申请日：1990-07-06

    Applicant: HITACHI LTD

    Inventor： KUROSAWA KENICHI ,  TANAKA SHIGEYA ,  NAKATSUKA YASUHIRO ,  BANDO TADAAKI

    IPC: G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177

    Abstract: PURPOSE:To improve throughput by providing a means to selectively execute plural instruction parallel processing and sequential processing. CONSTITUTION:Two instructions are read out from an instruction cache 100 when the value of a processing state flag PE116 in a processor status register 103 is turned on, and they are set at a first instruction register 104 and a second instruction register 105, and are processed in parallel with a first arithmetic unit 108 and a second arithmetic unit 109. Meanwhile, when the value of the flag PE116 is turned off, one instruction is read out from the instruction cache 100 to the first instruction register 104, and is processed with the first arithmetic unit 108, and also, the second arithmetic unit 109 is stopped, then, the sequential processing with the first arithmetic unit 108 is performed. In such a way, fast processing can be executed by using a high-level parallel processing function.

    RAPID INFERENCE SYSTEM FOR COMPILE TYPE KNOWLEDGE PROCESSING TOOL
    35.
    发明专利
    RAPID INFERENCE SYSTEM FOR COMPILE TYPE KNOWLEDGE PROCESSING TOOL 失效

    公开(公告)号：JPH02195434A

    公开(公告)日：1990-08-02

    申请号：JP1394489

    申请日：1989-01-25

    Applicant: HITACHI LTD

    Inventor： KUROSAWA KENICHI ,  SHIMADA MASARU ,  HIRAYAMA YOICHI ,  BANDO TADAAKI ,  MORI SEIZO

    IPC: G06F9/44 ,  G06F17/30 ,  G06N5/04

    Abstract: PURPOSE:To reduce pattern matching frequency and the overhead of interpretation and to improve the inference logic of a production system by one digit or more by narrowing down a rule to be executed and a frame to be referred by a dehashing method without storing an intermediate result and converting both the rule and frame into a machine instruction. CONSTITUTION:The knowledge base of the rapid inference system is constituted of a condition part for instructing an addaptive condition, a rule consisting of the condition part and execution for instructing the execution of action and a fact capable of obtaining a value, and stored in a storage part. The machine instruction stored in the storage device is executed by a processor and the processor converts the instruction into a machine instruction string capable of executing a fact to execute inference. The fact of the compile type knowledge rule is constituted of a frame consisting of plural attributes capable of obtained values and the frame is converted into a machine instruction string to be executed by the processor to execute the inference.

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