公开(公告)号：JP2004326799A

公开(公告)日：2004-11-18

申请号：JP2004128842

申请日：2004-04-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CHUNG VICENTE ENRIQUE ,  JOYNER JODY BERN ,  LEWIS JERRY DON

IPC: G06F15/173 ,  G06F9/00 ,  G06F13/12 ,  G06F13/36 ,  G06F15/16

CPC classification number: G06F15/17337

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for providing a processor book of a multiprocessor used as a building block for a large-scale data processing system. SOLUTION: The processor book is generated by using two 4 way-multichip modules (MCM). First and second MCM are constructed by using regular wiring between processors. Outer buses of respective chips in first MCM are connected to buses of corresponding chips of second MCM, and additional wiring which connects them reversely in a similar way is provided. The respective processors of first MCM can substantially directly access distributed memory structure elements of next MCM, which do not have affinity, by additional wiring. The processor book is plugged in a processor rack constituted to receive a plurality of the processor books. A plurality of the processor books collectively constitute the large-scale data processing system. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004220581A

公开(公告)日：2004-08-05

申请号：JP2003421698

申请日：2003-12-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  GUY LYNN GUTHRIE ,  STARKE WILLIAM JOHN

IPC: G06F12/08 ,  G06F3/00 ,  G06F12/02 ,  G06F12/10 ,  G06F13/12 ,  G06F13/14

CPC classification number: G06F13/124 ,  G06F12/0835

Abstract: PROBLEM TO BE SOLVED: To provide an improved processor, a data processing system and a data processing method. SOLUTION: An integrated circuit such as the processor includes a substrate and an integrated circuit element formed in the substrate. The integrated circuit element includes a processor core executing an instruction, an interconnect interface coupled to the processor core and supporting a communication between the processor core and a system interconnect external to the integrated circuit and, at least, a part of an external communication adapter coupled to the processor core and supporting input/output communication via an input/output communication link. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：提供改进的处理器，数据处理系统和数据处理方法。 解决方案：诸如处理器的集成电路包括衬底和形成在衬底中的集成电路元件。 集成电路元件包括执行指令的处理器核心，耦合到处理器核心的互连接口，并且支持处理器核心与集成电路外部的系统互连之间的通信，并且至少部分外部通信适配器耦合 到处理器核心并通过输入/输出通信链路支持输入/输出通信。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：JP2004192622A

公开(公告)日：2004-07-08

申请号：JP2003390008

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F9/46 ,  G06F12/02 ,  G06F15/167 ,  G06F15/173 ,  G06F15/76 ,  H04L12/28 ,  H04L12/56

CPC classification number: G06F15/173 ,  H04W28/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor possesses an exclusive right to store to a sector within each PCR within a cluster network and has continuous access to read the PCR contents of itself. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, makes all other processors within the cluster network to be able to quickly see the change within the PCR data and bypasses a cache subsystem. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004192619A

公开(公告)日：2004-07-08

申请号：JP2003389995

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  WILLIAMS DEREK EDWARD ,  KENNETH LEE WRIGHT

IPC: G06F15/17 ,  G06F9/00 ,  G06F9/30 ,  G06F9/52 ,  G06F12/02 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173

CPC classification number: G06F9/30101

Abstract: PROBLEM TO BE SOLVED: To provide an improved data processing system architecture reducing waiting time of communication between physically separating processors, reducing bus bandwidth consumption, and releasing the bus bandwidth for a general data transfer between the processor and a hierarchical memory system. SOLUTION: The identical processing communication information useful in pipelined multiprocessing or parallel multiprocessing is stored in each processor communication register (PCR). Each processor updates its exclusive sector within all of the PCRs, makes all other processors to be able to quickly see the change within the PCR data and bypasses a cache subsystem. BY temporarily restricting access to the information or by forcing all the processors to continuously compete and providing processor communication quickly transferred to all the processors, efficiency of the multiprocessor system can be improved. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004185610A

公开(公告)日：2004-07-02

申请号：JP2003388587

申请日：2003-11-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ARIMILLI RAVI KUMAR ,  GOODMAN BENJIMAN LEE ,  JOYNER JODY BERN

IPC: G06F12/08 ,  G06F12/00 ,  G06F12/02 ,  G06F13/40 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

CPC classification number: G06F13/4022 ,  G06F12/0831

Abstract: PROBLEM TO BE SOLVED: To provide a method for avoiding livelock within a multiprocessor data processing system when there are multiple concurrent clone operations to same memory data locations within a data processing system. SOLUTION: A set of tokens are defined within the memory cloner use prior to conducting a clone operation on the fabric. The tokens include a source token and a destination token. The tokens are issued on the fabric by a memory cloner prior to initiating the data clone operation. The tokens discover the availability of a source address and a destination address required to complete the clone operation. Once the response to the destination address token indicates that the destination address is not currently being utilized by another memory cloner to conduct another data clone operation, the memory cloner issues a command to initiate the memory clone operation. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2003030171A

公开(公告)日：2003-01-31

申请号：JP2002164635

申请日：2002-06-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  FIELDS JAMES STEPHEN JR

IPC: G06F9/52 ,  G06F12/08 ,  G06F15/177

CPC classification number: G06F12/0817 ,  G06F12/0813

Abstract: PROBLEM TO BE SOLVED: To provide an NUMA architecture having improved queuing, storage communication efficiency. SOLUTION: A non-uniform memory access(NUMA) computer system includes at least one remote node and a home node coupled by node mutual connection. The home node includes a home system memory and a memory controller. In response to the reception of a data request from the remote node, the memory controller determines whether to impart the exclusive ownership or non- exclusive ownership of request data designated in the data request by referring to history information showing previous data access occurring in the remote node. The memory controller transmits the request data and the instruction of the exclusive ownership or non-exclusive ownership to the remote node, next.

Abstract translation: 要解决的问题：提供具有改进的排队，存储通信效率的NUMA架构。 解决方案：非均匀存储器访问（NUMA）计算机系统包括至少一个远程节点和通过节点相互连接耦合的归属节点。 家庭节点包括家庭系统存储器和存储器控制器。 响应于来自远程节点的数据请求的接收，存储器控制器通过参考表示在该远端中发生的先前数据访问的历史信息来确定是否赋予在数据请求中指定的请求数据的专有所有权或非排他所有权 节点。 接下来，存储器控制器将请求数据和独占所有权或非排他所有权的指令发送到远程节点。

公开(公告)号：JPH11328027A

公开(公告)日：1999-11-30

申请号：JP3178799

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain a cache coherence protocol which uses a tagged coherence state to increase the memory band width without immediately writing back a change value to a system memory. SOLUTION: When a tagged state is assigned to a cache line which is loaded with the change value latest, the history state related to the tagged state which is moved between caches (in the horizontal direction) can be used furthermore. This system is also applied to a multi-processor computer system having clustered processing units, and a tagged state is applied t one of cache lines in each group of caches which support different processing unit clusters. Priority levels are assigned to different cache states, and they include tagged states for response to requests which access corresponding memory blocks. Because of use of a crossbar, a tagged intermediary response is transferred to only selected caches which are affected by this intermediary response.

公开(公告)号：JPH11328025A

公开(公告)日：1999-11-30

申请号：JP3163399

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To obtain an improved method for maintaining data coherency by determining whether or not a 1st cache should be updated according to the operation mode of the 1st cache in response to the detection of data transfer to remotely sent and including a 2nd data item. SOLUTION: A L2 cache 14 includes a cache controller 36. The cache controller 36 manages the storage and retrieval of data in a data array 34 and manages the update of a cache directory 32 in response to a signal received from a relative L1 cache and transaction snooped through an interconnection line. Then, a read request is put in an entry in a read queue 50. The cache controller 36 services the read request by supplying requested data to the relative L1 cache and then, removes the read request from the read queue 50.

公开(公告)号：JPH11328024A

公开(公告)日：1999-11-30

申请号：JP3158699

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To improve the inclusivity of a vertical cache hierarchy by mounting a modified MESI cache coherency protocol in a cache which can be accessed. SOLUTION: A coherency state field 208 of each entry in a cache director 204 is initially set to an ineffective state when a system is powered on and indicates that the both of a tag field 206 and data stored in relative cache lines in a cache memory 202 are ineffective. Thereafter, the coherency state field 208 can be updated to the coherency state in a deformed MESI coherency protocol. A cache controller 214 responds variously to snooped system bus operation and an L3 cache releases the allocation of a designated cache line of the cache memory.

公开(公告)号：JPH11328016A

公开(公告)日：1999-11-30

申请号：JP3153599

申请日：1999-02-09

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To maintain the coherency between a data cache and an instruction cache which are separated by cleaning a designated cache entry in the data cache and instructing to invalidate the designated cache entry of the instruction cache. SOLUTION: Combined instructions are executed repeatedly for each of cache blocks included in the whole page 224 of a memory or in the plural pages of the memory to update a graphic display and a display buffer. When a mode bit 214 is set, icbi from a local processor is handled as no operation. In different kind of a system, snooped icbi is handled as the icbi even when the mode bit 214 is set. Instead of the above, the contents at a cache position (x) are copied to another position (y) and the corresponding cache position in a horizontal cache is invalidated.