公开(公告)号：CA1053378A

公开(公告)日：1979-04-24

申请号：CA224582

申请日：1975-04-11

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L21/76

Abstract: METHOD AND DEVICE FOR REDUCING SIDEWALL CONDUCTION IN RECESSED OXIDE FET ARRAYS Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistor (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide thereon. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

公开(公告)号：FR2357066A1

公开(公告)日：1978-01-27

申请号：FR7716800

申请日：1977-05-26

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/52 ,  H01L29/417 ,  H01L29/78 ,  H01L21/283

公开(公告)号：CA754681A

公开(公告)日：1967-03-14

申请号：CA754681D

Applicant: IBM

Inventor： DENNARD ROBERT H ,  JULIUSBURGER HANS Y ,  SIMAITIS GERVYDAS E ,  NAKAGAWA NORIYUKI

公开(公告)号：DE1228657B

公开(公告)日：1966-11-17

申请号：DEJ0024911

申请日：1963-12-12

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DENNARD ROBERT H

IPC: H03D1/24 ,  H04B1/68 ,  H04L27/02

Abstract: 1,031,596. Vestigial sideband transmission systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 21, 1963 [Dec. 18, 1962], No. 45929/63. Heading H3R. In a vestigial side-band suppressed carrier system for transmitting data signals and particularly in such a system where a repetitive data pattern is transmitted which contains no D.C. or low frequency A.C. components, the difficulty of reconstituting the carrier for synchronous detection at the receiver is overcome by adding either a D.C. signal or a low frequency A.C. signal to the data signal before application to a balanced modulator whereby either a small amount of carrier or two side-band signals equally disposed on either side of the carrier position are transmitted. The data signals are applied via unit 5, Fig. 2, and L.P. filter 6 to a balanced modulator 7 which also receives an input at frequency fc from carrier oscillator 8, the output of the modulator is applied via a vestigial side-band filter 9 to the transmission path. The response of the vestigial side-band filter is such that no upper sideband signals greater in frequency than fc + f1 are transmitted. The unit 5 may take several forms, e.g. in the arrangement shown in Fig. 3 a D.C. signal from source 5A is added to the data signals in summing circuit 5C and this signal produces an unbalance in the modulator which allows a small amount of carrier signal to be transmitted. In the arrangement shown in Fig. 5, signal generator 20 develops a signal which is applied via logic circuitry to a summing circuit 26 in which it is added to the data signal. The resultant signal after modulation produces two side-bands fc - f3 and fc + f3 which are sufficiently close to the carrier for the upper side-band to be passed by the vestigial sideband filter. At the receiver the signals are amplified and applied to a filter 12 which is the complement of the V.S.B. filter and hence passes signals in the range fc - f1 to fc + f1, these signals are applied to a square low detector which produces an output signal at 2fc. This signal after clipping is applied via a narrow band filter 15, delay network 16, in which its phase may be adjusted, limiter 17 and " divide by two " circuit 18 to a balanced demodulator 10 to which the input signal is also applied.