公开(公告)号：US3899363A

公开(公告)日：1975-08-12

申请号：US48403374

申请日：1974-06-28

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L27/08

CPC classification number: H01L21/76216 ,  H01L21/00 ,  H01L21/30608 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/7621 ,  Y10S148/051

Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

Abstract translation: 使用硅半导体场效应晶体管（FET）制造用于高速存储器和逻辑应用的紧密集成的集成电路阵列，其通过完全凹陷的氧化物隔离区彼此电隔离。 制造方法的特征在于将凹陷氧化物的侧壁的有害源降低到漏极导通的程度比FET的主沟道的电流更小。 离子注入用于在邻近侧壁区域和凹陷氧化物下面的硅衬底中提供额外的掺杂浓度。 凹陷氧化物下面的多余掺杂剂用作寄生通道阻挡层。 在其中形成凹陷的氧化物之前，通过将硅衬底中的倾斜侧壁植入，来促进侧壁掺杂。 倾斜的侧壁通过利用与<100>取向的p导电型基底组合的各向异性蚀刻来实现。

公开(公告)号：FR2351502A1

公开(公告)日：1977-12-09

申请号：FR7710334

申请日：1977-03-30

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/31 ,  H01L27/04

Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

公开(公告)号：CA1116313A

公开(公告)日：1982-01-12

申请号：CA326909

申请日：1979-05-04

Applicant: IBM

Inventor： RIDEOUT VINCENT L

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/24

Abstract: PROCESS FOR PROVIDING SELF-ALIGNED DOPING REGIONS A process for providing ion-implanted regions in a substrate such as silicon beneath an existing layer such as silicon dioxide and being self-aligned to subsequently fabricated regions of said layer which includes providing a resist masking pattern above the existing layer wherein the resist masking pattern has vertical sidewalls (i.e., perpendicular to the upper surface of the substrate) or is undercut; ion-implanting impurities such as boron ions through the layer but not through the resist and portions of the layer beneath the resist, and depositing a layer of lift-off material such as aluminum on the existing layer and on the resist. The implantation step must be performed after providing the undercut resist masking pattern, but before depositing the layer of lift-off material in order to achieve the desired self-alignment feature. Because of the resist profile (i.e., vertical walls or being undercut) no lift-off material is deposited on the sidewalls of the resist and a gap is formed between the resist and that portion of the lift-off material which is above the existing layer. The resist pattern is removed along with the portion of the lift-off material layer deposited thereon. The nowexposed portion of the existing layer located beneath the previous resist pattern is then removed. Finally, the remaining regions of lift-off material are removed from above YO-977-022 the regions of the existing layer. The ion-implanted regions occur in the substrate beneath the remaining portions of the existing layer, are self-aligned to the boundaries of said portions, and correspond to a negative image of the original undercut resist masking pattern.

公开(公告)号：CA1079866A

公开(公告)日：1980-06-17

申请号：CA271024

申请日：1977-02-03

Applicant: IBM

Inventor： RIDEOUT VINCENT L

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/22 ,  H01L21/31

Abstract: FET ONE-DEVICE MEMORY CELLS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON Fabricating an integrated circuit array of FET one-device memory cells which includes providing a semisemiconductive substrate of a first conductive type; delineating field insulation regions; delineating polycrystalline silicon gate regions employing an oxidation barrier masking layer; introducing active impurities of a second and opposite conductive type into predetermined regions of the substrate to provide doped bit lines (FET drains), connection regions (FET sources), and lower conductive electrodes of the storage capacitors; next delineating upper poycrystalline silicon electrodes of the storage capacitors; growing silicon dioxide insulation over all portions of the structure except over the FET gate regions which are protected by the oxidation barrier masking layer; removing the oxidation barrier masking layer over the FET gates with an etchant; delineating contact holes to polycrystalline silicon capacitor electrodes and to FET sources and drains in circuits peripheral to the array of memory cells; and delineating the metallic-type high-conduc-tivity electrical interconnection word line pattern.

公开(公告)号：CA1078077A

公开(公告)日：1980-05-20

申请号：CA279093

申请日：1977-05-25

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/52 ,  H01L29/417 ,  H01L29/78 ,  H01L27/10 ,  H01L29/76

Abstract: SELF-REGISTERING METHOD OF FABRICATING FIELD EFFECT TRANSISTORS A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a selfregistering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer provides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line.

公开(公告)号：FR2276691A1

公开(公告)日：1976-01-23

申请号：FR7516564

申请日：1975-05-23

Applicant: IBM

Inventor： DENNARD ROBERT M ,  RIDEOUT VINCENT L ,  WALKER EDWARD J

IPC: H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L27/088 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L21/74 ,  H01L29/76 ,  G11C11/34

Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

公开(公告)号：DE2961594D1

公开(公告)日：1982-02-11

申请号：DE2961594

申请日：1979-05-03

Applicant: IBM

Inventor： RIDEOUT VINCENT L

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L21/00

Abstract: A process for providing ion-implanted regions (6) in a semi-conductive substrate (2) such as silicon beneath an existing layer (3) such as silicon dioxide and being self-aligned to subsequently fabricated regions of said layer which includes providing a resist masking pattern (4) above the existing layer (3) wherein the resist masking pattern has vertical sidewalls (i.e., perpendicular to the upper surface of the substrate) or is undercut; ion-implanting impurities such as boron ions through the layer (3) but not through the resist (4) and portions of the layer beneath the resist; and depositing a layer of lift-off material (7) such as aluminum on the existing layer and on the resist. The implantation step must be performed after providing the undercut resist masking pattern, but before depositing the layer of lift-off material (7) in order to achieve the desired self-alignment feature. Because of the resist profile (i.e., vertical walls or being undercut) no lift-off material is deposited on the sidewalls of the resist and a gap (8) is formed between the resist (4) and that portion of the lift-off material (7) which is above the existing layer. The resist pattern is removed along with the portion of the lift-off material layer deposited thereon. The nowexposed portion of the existing layer located beneath the previous resist pattern is then removed. Finally, the remaining regions of lift-off material are removed from above the regions of the existing layer.

公开(公告)号：CA1082371A

公开(公告)日：1980-07-22

申请号：CA278402

申请日：1977-05-13

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/50 ,  H01L21/44

Abstract: FIELD EFFECT TRANSISTOR WITH SELF-ALIGNED GATE A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self aligned on its sides with respect to the non-con-ductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double selfalignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

公开(公告)号：FR2340622A1

公开(公告)日：1977-09-02

申请号：FR7700642

申请日：1977-01-05

Applicant: IBM

Inventor： RIDEOUT VINCENT L

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L29/92

Abstract: Field effect transistors of both enriched and depleted types, i.e. normally conducting or cut-off, are produced; several fet's can be formed on the same substrate and included in integrated circuits. The fet element has a silicon gate and includes a capacitor in the build up on the substrate. Five stages of lithographic masking are employed starting with isolation of the transistor regions from neighbouring components, source and drain regions are automatically aligned with respect to the gate area and one electrode of the associated capacitor. Conducting surfaces are laid down in the final masking stage.

公开(公告)号：CA1095179A

公开(公告)日：1981-02-03

申请号：CA282911

申请日：1977-07-18

Applicant: IBM

Inventor： DENNARD ROBERT H ,  RIDEOUT VINCENT L

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06 ,  H01L21/94 ,  H01L21/31

Abstract: METHOD OF MAKING FIELD EFFECT TRANSISTOR A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implatation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps. This single doping step is facilitated by use of a thick field isolation oxide which is chemically vapor deposited at a relatively low processing temperature after performing the common doping step.