公开(公告)号：ES2003376A6

公开(公告)日：1988-11-01

申请号：ES8602599

申请日：1986-10-15

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L29/78

Abstract: DISPOSITIVO DE MEMORIA DINAMICA Y METODO PARA FABRICARLO, EN DONDE EL DISPOSITIVO COMPRENDE UN SUSTRATO DE SILICIO MONOCRISTALINO PB, UN CONDENSADOR DE DEPRESION, UNA CAPA DE SILICIO EPITAXIAL MONOCRISTALINO, UN TRANSISTOR DE ACCESO Y UNA REGION DE SILICIO POLICRISTALINO NB, MIENTRAS QUE EL METODO COMPRENDE SITUAR UNA DEPRESION EN EL SUSTRATO, HABILITAR UNA PELICULA DE SIO2/SI3N4/SIO2 PARA AISLAR EL CONDENSADOR, SOBREPONER AL SILICIO POLICRISTALINO UNA DELGADA CAPA DE SIO2, APLICAR UNA CAPA DE SILICIO EPITAXIAL P SOBRE EL SUSTRATO Y LA CAPA DE SIO2, Y COLOCAR EL TRANSISTOR DE ACCESO ENCIMA DEL CONDENSADOR, CONECTANDO UN MATERIAL IMPURIFICADO NB LA REGION DE FUENTE DEL TRANSISTOR CON EL SILICIO POLICRISTALINO Y PUDIENDO DISPONERSE UNA REGION P IMPURIFICADA ENCIMA DE LA SUPERFICIE DE LA DEPRESION. EL INVENTO ES APLICABLE A MEMORIAS ELECTRONICAS DINAMICAS DE ACCESO ALEATORIO.

公开(公告)号：CA1232362A

公开(公告)日：1988-02-02

申请号：CA518033

申请日：1986-09-11

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/72

Abstract: A DYNAMIC MEMORY DEVICE HAVING A SINGLE-CRYSTAL TRANSISTOR ON A TRENCH CAPACITOR STRUCTURE AND A FABRICATION METHOD THEREFOR Dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO2/Si3N4/Sio2 is provided for the capacitor storage insulator. A thin layer of SiO2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：ZA8606625B

公开(公告)日：1987-06-24

申请号：ZA8606625

申请日：1986-09-01

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01C ,  H01L

CPC classification number: H01L27/10861 ,  H01L21/743 ,  H01L21/8221 ,  H01L27/10832