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    5.
    发明专利
    未知

    公开(公告)号：DE3688231T2

    公开(公告)日：1993-11-04

    申请号：DE3688231

    申请日：1986-08-22

    Applicant: IBM

    Inventor： LU NICKY CHAU-CHUN

    IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/82

    Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

    6.
    发明专利
    未知

    公开(公告)号：MX165273B

    公开(公告)日：1992-11-04

    申请号：MX867587

    申请日：1987-10-02

    Applicant: IBM

    Inventor： LU NICKY CHAU-CHUN ,  MACHESNEY BRIAN JOHN

    IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

    Abstract: A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands (18) which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor (80, 84, 98) formed in monocrystalline silicon (30) stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window (52) for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

    Voltage boosting circuits for dynamic memories
    7.
    发明专利
    Voltage boosting circuits for dynamic memories 未知

    公开(公告)号：HK203796A

    公开(公告)日：1996-11-15

    申请号：HK203796

    申请日：1996-11-07

    Applicant: IBM

    Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

    IPC: G11C11/408 ,  H03K5/02 ,  G11C11/407

    Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

    8.
    发明专利
    未知

    公开(公告)号：DE3688231D1

    公开(公告)日：1993-05-13

    申请号：DE3688231

    申请日：1986-08-22

    Applicant: IBM

    Inventor： LU NICKY CHAU-CHUN

    IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/82

    Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

    EPITAXIAL LAYER MASK
    9.
    发明专利
    EPITAXIAL LAYER MASK 未知

    公开(公告)号：AU594200B2

    公开(公告)日：1990-03-01

    申请号：AU7926887

    申请日：1987-10-01

    Applicant: IBM

    Inventor： LU NICKY CHAU-CHUN ,  MACHESNEY BRAIN JOHN

    IPC: H01L27/04 ,  G11C11/24 ,  H01L21/20 ,  H01L21/205 ,  H01L21/74 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    Abstract: A fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands (18) which forms a self-aligned contact window in the epitaxial layer. Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor (80, 84, 98) formed in monocrystalline silicon (30) stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window (52) for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit for logic circuits and static-RAM cell.

    10.
    发明专利
    未知

    公开(公告)号：BR8803628A

    公开(公告)日：1989-02-14

    申请号：BR8803628

    申请日：1988-07-20

    Applicant: IBM

    Inventor： HWANG WEI ,  LU NICKY CHAU-CHUN

    IPC: H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L29/78 ,  G11C11/34 ,  G11C11/21

    Abstract: A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate (10) and an epitaxial layer (10) thereon including a vertical transistor (14) disposed in a shallow trench (100) stacked above and self-aligned with a capacitor in a deep trench (16). The stacked vertical transistor (4) has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor (14) is a lightly-doped drain structure (21) connected to a bitline element (22). The source (24) of the transistor, located at the bottom of the transistor trench (100) and on top of the center of the trench capacitor (16), is self-aligned and connected to polysilicon (28) contained inside the trench capacitor. Three sidewalls of the access transistor (14) are surrounded by thick oxide isolation (50) and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well (26) and uses the n-well and heavily-doped substrate (10) as the capacitor counter-electrode plate. The cell storage node is the polysilicon (28) inside the trench capacitor. The fabrication method includes steps for growing epitaxial layers wherein an opening (100) is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

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