公开(公告)号：JP2007129235A

公开(公告)日：2007-05-24

申请号：JP2006299336

申请日：2006-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/786 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78684

Abstract: PROBLEM TO BE SOLVED: To provide a FinFET including a gate electrode formed so as to cover a channel region of a semiconductor fin, and to provide a method of manufacturing the same.
SOLUTION: This semiconductor fin has a crystallographic orientation and a piezoresistance coefficient intrinsic to an axial direction. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. For this purpose, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region which complement the piezoresistance coefficient intrinsic to the axial direction.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种FinFET，其包括形成为覆盖半导体鳍片的沟道区域的栅电极，并提供其制造方法。 解决方案：该半导体鳍具有晶体取向和轴向固有的压阻系数。 形成栅电极，该固有应力确定为影响并优选地优化沟道区内的载流子迁移率。 为此，固有应力优选地在栅极电极和半导体鳍片沟道区域内提供与轴向固有的压阻系数相互补充的感应轴向应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007129223A

公开(公告)日：2007-05-24

申请号：JP2006294911

申请日：2006-10-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  UTOMO HENRY K

IPC: H01L29/786 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/7843 ,  H01L29/7845

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure using a semiconductor substrate having a channel region, and to provide a manufacturing method thereof. SOLUTION: A gate electrode is arranged on the semiconductor substrate. A spacer is arranged adjacently to a sidewall of the gate electrode. This spacer is formed of a material having a modulus of about 10-50 GPa. The modulus provides enhanced stress within the channel region. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用具有沟道区域的半导体衬底的半导体结构，并提供其制造方法。 解决方案：栅电极设置在半导体衬底上。 间隔件被布置成与栅电极的侧壁相邻。 该间隔物由具有约10-50GPa的模量的材料形成。 该模量在通道区域内提供增强的应力。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2004193596A

公开(公告)日：2004-07-08

申请号：JP2003396240

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  CHIDAMBARRAO DURESETI ,  BAIE XAVIER ,  MANDELMAN JACK A ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.
SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while the stress is tensile stress in an NFET device. The stress is produced by a compressive film 34 located in an area 32 under the channel. The compressive film pushes up the channel 22 which bends the channel. In the PFET device, the compressive film is arranged under the edge 31 of the channel (e.g., under a source or drain) which compresses the upper part 22A of the channel. In the NFET device, the compressive film is arranged under the center 40 of the channel (e.g., under the gate) which pulls the upper part 22A of the channel. Therefore, both the NFET device and the PFET device can be strengthened. A method for manufacturing these devices is included.
COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：WO2007103854A3

公开(公告)日：2008-04-10

申请号：PCT/US2007063275

申请日：2007-03-05

Applicant: IBM ,  CHIDAMBARRAO DURESETI

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7842

Abstract: An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate (600), comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices (620) on the first areas and second type devices (630) on the second areas, wherein the first type devices (620) are parallel or perpendicular to the second type devices (630), and the first type devices (620) comprise a first current flow (621) and a second current flow (622) orthogonal to each other, wherein the carrier mobilities of the first (621) and second (622) current flows are equal to each other. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).

Abstract translation: 本发明的实施例的集成电路包括混合取向衬底（600），其包括具有第一结晶取向的第一区域和具有第二结晶取向的第二区域。 第一区域的第一晶体取向不平行或垂直于第二区域的第二晶体取向。 集成电路还包括第一区域上的第一类型设备（620）和第二区域上的第二类型设备（630），其中第一类型设备（620）平行或垂直于第二类型设备（630），并且 第一类型装置（620）包括彼此正交的第一电流（621）和第二电流（622），其中第一（621）和第二（622）电流的载流子迁移率彼此相等。 具体地，第一类型器件包括p型场效应晶体管（PFET），第二类型器件包括n型场效应晶体管（NFET）。

公开(公告)号：WO2005027192A3

公开(公告)日：2006-12-21

申请号：PCT/US2004028163

申请日：2004-08-30

Applicant: IBM ,  DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

Inventor： DOKUMACI OMER ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  YANG HAINING S

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

Abstract: A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

Abstract translation: 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO2005043590A3

公开(公告)日：2006-09-21

申请号：PCT/US2004034528

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括用于pFET（40）和nFET（45）的沟道。 在nFET沟道的沟道中生长SiGe层（45a），并且在pFET沟道中生长Si：C层（40a）。 SiGe和Si：C匹配下层Si层（15）的晶格网络，以在上覆的生长的外延层（60）中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在进一步的实施中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：JP2007300103A

公开(公告)日：2007-11-15

申请号：JP2007113990

申请日：2007-04-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MOCUTA ANDA C ,  CHIDAMBARRAO DURESETI ,  DONATON RICARDO A ,  KERN RIM ,  ONSONGO DAVID MASARA

IPC: H01L21/20 ,  H01L21/338 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L29/812

CPC classification number: H01L21/823807 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/78687

Abstract: PROBLEM TO BE SOLVED: To reduce the formation of misfit dislocation that may reduce the charge mobility and device performance. SOLUTION: There is provided a method of manufacturing a semiconductor structure and a semiconductor device, more specifically, an N-type FET device. The device includes a stress receiving layer provided on a stress inducing layer via a material at an interface between the layers, which reduces the occurrence and propagation of misfit dislocation in the structure. The stress receiving layer includes silicon (Si), the stress inducing layer includes silicon-germanium (SiGe), and the material includes carbon given by doping both layers during the period of the formation of the device. The carbon can be doped over the entire SiGe layer. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：减少可能降低电荷迁移率和器件性能的失配位错的形成。 解决方案：提供一种制造半导体结构和半导体器件的方法，更具体地说，涉及一种N型FET器件。 该装置包括通过层之间的界面处的材料在应力诱导层上提供的应力接收层，这减少了结构中失配位错的发生和传播。 应力接收层包括硅（Si），应力诱导层包括硅锗（SiGe），并且该材料包括在器件形成期间通过掺杂两层给出的碳。 碳可以掺杂在整个SiGe层上。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007294950A

公开(公告)日：2007-11-08

申请号：JP2007103478

申请日：2007-04-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  JOHN JOSEF ELLIS-MONAHAN ,  GREENE BRIAN J

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L27/1203 ,  H01L21/823814

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a transistor device with a dopant depth which is extended and increased so as to have no effect on a channel region of a transistor.
SOLUTION: The method comprises: (a) a step of providing a substrate comprising a semiconductor-on-insulator structure ("SOI") layer separated from a bulk region in the substrate by an embedded dielectric layer; (b) a step of performing a first implantation to the SOI layer in order to attain a predetermined concentration of dopant in an interface of the SOI layer to the embedded dielectric layer; and (c) a step of performing a second implantation to the SOI layer in order to attain a predetermined concentration of dopant in a polycrystalline semiconductor gate conductor ("poly gate") as well as in a source region and a drain region which are arranged to be adjacent to the poly gate. The maximum depth of the first implantation is deeper than the maximum depth of the second implantation.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成具有扩展和增加的掺杂剂深度的晶体管器件的方法，以便对晶体管的沟道区域没有影响。 解决方案：该方法包括：（a）提供包括绝缘体上半导体结构（“SOI”）层的衬底的步骤，该衬底通过嵌入的电介质层与衬底中的本体区域分离; （b）为了在SOI层与嵌入介电层的界面中获得预定浓度的掺杂剂，对SOI层进行第一次注入的步骤; 以及（c）为了在多晶半导体栅极导体（“多晶硅”）以及源极区和漏极区中排列的多个半导体栅极导体（“多晶硅”）以及源极区和漏极区域中的掺杂剂浓度达到预定浓度，对SOI层进行第二注入的步骤 与多门相邻。 第一植入的最大深度比第二植入的最大深度更深。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007158323A

公开(公告)日：2007-06-21

申请号：JP2006311038

申请日：2006-11-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHIDAMBARRAO DURESETI ,  KERN RIM ,  GREENE BRIAN J

IPC: H01L29/786 ,  H01L21/76 ,  H01L29/78

CPC classification number: H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

Abstract: PROBLEM TO BE SOLVED: To provide a transistor having a stress-producing dielectric element which underlies the entire undersurface of an active semiconductor region.
SOLUTION: A compressive stress is applied to a channel region of a PFET by a structure including an independent stress-producing dielectric element that entirely underlies the bottom surface of an active semiconductor region in which a source, a drain and a channel region of the PFET are disposed. Specifically, the stress-producing dielectric element includes a region of a collapsed oxide which contacts the entire bottom surface of the active semiconductor region so that it has an area of the same spread as an area of the bottom surface. Bird beak-like oxide regions at the edges of the stress-producing dielectric element apply an upward force to the edges of the stress-producing dielectric element to provide a compressive stress to the channel region of the PFET.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有产生应力的介电元件的晶体管，其在有源半导体区域的整个下表面的下方。 解决方案：通过包括独立的产生应力的电介质元件的结构将压应力施加到PFET的沟道区域，该电介质元件完全位于有源半导体区域的底表面之下，其中源极，漏极和沟道区域 的PFET。 具体而言，应力产生用电介质元件包括与活性半导体区域的整个底面接触的塌陷氧化物的区域，使得其具有与底面的面积相同的面积。 产生应力的电介质元件边缘处的鸟形喙状氧化物区向产生应力的电介质元件的边缘施加向上的力，以向PFET的沟道区提供压缩应力。 版权所有（C）2007，JPO＆INPIT