公开(公告)号：WO2008014228A3

公开(公告)日：2008-09-04

申请号：PCT/US2007074169

申请日：2007-07-24

Applicant: IBM ,  CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

Inventor： CHAKRAVARTI ASHIMA B ,  CHIDAMBARRAO DURESETI ,  HOLT JUDSON R ,  LIU YAOCHENG ,  RIM KERN

IPC: H01L21/336

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si: C and polishing an etching the Si: C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si: C with sufficiently high substitutional carbon content are inherently non-selective.

Abstract translation: 为了通过向NFET的沟道区施加张力而有效地增加电子迁移率，具有超过1％的替代碳含量的嵌入式硅碳（Si：C）通过过度填充由晶体管栅极结构形成的间隙或沟槽来实现 与Si：C并且在超级大马士革工艺中将Si：C蚀刻到凸起栅极结构的表面或其下方，即使能够沉积的工艺仅在晶体管源极和漏极之上的选定区域中留下Si：C 具有足够高取代碳含量的Si：C本质上是非选择性的。

公开(公告)号：WO2007025259A2

公开(公告)日：2007-03-01

申请号：PCT/US2006033582

申请日：2006-08-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

Inventor： CHIDAMBARRAO DURESETI ,  ADAM THOMAS N

IPC: H01L29/00

CPC classification number: H01L29/7378 ,  H01L29/161 ,  H01L29/165

Abstract: The present invention relates to a high performance heterojunction bipolar transistor (HBT) having abase region with a SiGe-containing layer therein. The SiGe-containing layer is not more than about 100 ran thick and has a predetermined critical germanium content. The SiGe-containing layer further has an average germanium content of not less than about 80% of the predetermined critical germanium content The present invention also relates to a method for enhancing carrier mobility in a HBT having a SiGe-containing base layer, by uniformly increasing germanium content in the base layer so that the average germanium content therein is not less than 80% of a critical germanium content, which is calculated based on the thickness of the base layer, provided that the base layer is not more than 100 nm thick.

Abstract translation: 本发明涉及一种具有其中含SiGe的层的碱性区的高性能异质结双极晶体管（HBT）。 含SiGe的层的厚度不超过约100埃，具有预定的临界锗含量。 含SiGe的层还具有不小于预定临界锗含量的约80％的平均锗含量本发明还涉及通过均匀增加的具有含SiGe的基底层来提高具有含SiGe的基底层的HBT中的载流子迁移率的方法 基底层中的锗含量，使得其中的平均锗含量不小于基于基底层的厚度计算的临界锗含量的80％，条件是基底层不大于100nm厚。

公开(公告)号：WO2006063060A3

公开(公告)日：2006-11-16

申请号：PCT/US2005044281

申请日：2005-12-08

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  LI YING ,  MALIK RAJEEV ,  NARASIMHA SHREESH ,  YANG HAINING ,  ZHU HUILONG

IPC: H01L21/31 ,  H01L23/58

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET (300) and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner (360) to the device and applying a second silicon nitride liner (370) adjacent the fast silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel (330) beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET（300）提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫（360）施加到器件上，并施加与快速氮化硅衬垫相邻的第二氮化硅衬垫（370） ，其中所述第一和第二氮化硅衬垫中的至少一个在所述第一和第二氮化硅衬垫中的至少一个下方的硅沟道（330）中引起横向应力。

公开(公告)号：WO2006065759A3

公开(公告)日：2007-06-14

申请号：PCT/US2005044957

申请日：2005-12-13

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER H ,  DORIS BRUCE B ,  GLUSCHENKOV OLEG ,  ZHU HUILONG

IPC: H01L21/84 ,  H01L27/01

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

Abstract: The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer, and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si 3 N 4 .

Abstract translation: 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层，以及第二层叠堆叠 所述第二层叠堆叠包括位于所述衬底顶部的拉伸电介质层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：WO2005043590A3

公开(公告)日：2006-09-21

申请号：PCT/US2004034528

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H01L29/778 ,  H01L31/036 ,  H01R4/64

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66621 ,  Y10S438/933

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET (40) and an nFET (45). An SiGe layer (45a) is grown in the channel of the nFET channel and a Si:C layer (40a) is grown in the pFET channel. The SiGe and Si:C match lattice network of the underlying Si layer (15) to create a stress component in an overlying grown epitaxial layer (60). In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In further implementation, the SiGe layer grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括用于pFET（40）和nFET（45）的沟道。 在nFET沟道的沟道中生长SiGe层（45a），并且在pFET沟道中生长Si：C层（40a）。 SiGe和Si：C匹配下层Si层（15）的晶格网络，以在上覆的生长的外延层（60）中产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。 在进一步的实施中，SiGe层在nFET和pFET沟道中生长。 在这种实现中，pFET通道中的应力水平应该大于3GPa。

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：WO2007140288A3

公开(公告)日：2008-04-24

申请号：PCT/US2007069720

申请日：2007-05-25

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

Inventor： CHIDAMBARRAO DURESETI ,  HENSON WILLIAM K ,  NG HUNG Y ,  RIM KERN ,  WANN CLEMENT H

IPC: H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76283

Abstract: The present invention relates to semiconductor-on-insulator (SOI) substrates having device regions (2, 4, 6), each comprises a base semiconductor substrate layer (12) and a semiconductor device layer (16) and a buried insulator layer (14) between. The semiconductor device layer (16) supported by vertical insulating pillars (22), each having a ledge extending between the base semiconductor substrate layer (12) and the semiconductor device layer (16). The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a "floating" semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap (15) and is supported by the vertical insulating pillars (22). The air gap (15) is preferably formed by selective removal of a sacrificial layer (13) located between the base semiconductor substrate layer (12) and the semiconductor device layer (16).

Abstract translation: 本发明涉及具有器件区域（2,4,6）的绝缘体上绝缘体（SOI）衬底，每个衬底半导体衬底层（12）和半导体器件层（16）和掩埋绝缘体层（14） ）之间。 由垂直绝缘柱（22）支撑的半导体器件层（16）各自具有在基底半导体衬底层（12）和半导体器件层（16）之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙（15）与基底半导体衬底层间隔开并由垂直绝缘柱（ 22）。 气隙（15）优选通过选择性地去除位于基底半导体衬底层（12）和半导体器件层（16）之间的牺牲层（13）来形成。

公开(公告)号：WO2005043591A3

公开(公告)日：2007-06-21

申请号：PCT/US2004034562

申请日：2004-10-19

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  CHEN HUAJIE

IPC: H01L21/00 ,  H01L20060101 ,  H01L21/336 ,  H01L21/461 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10 ,  H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract translation: 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

公开(公告)号：WO2005017964A2

公开(公告)日：2005-02-24

申请号：PCT/US2004025152

申请日：2004-08-04

Applicant: IBM ,  CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

Inventor： CHEN HUAJIE ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG G ,  STEEGEN AN L ,  YANG HAINING S

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L

CPC classification number: H01L21/84 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Abstract translation: 提供集成电路的p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 第一应变施加到PFET的沟道区，而不是NFET通过位于仅仅PFET而不是NFET的源极和漏极区域中的晶格不匹配的半导体层，例如硅锗。 提供制造PFET和NFET的工艺。 在区域中蚀刻沟槽以成为PFET的源极和漏极区域，并且将晶格失配的硅锗层外延生长以向与其相邻的PFET的沟道区域施加应变。 可以在硅锗层上生长一层硅层，并从硅层形成硅化物以提供低电阻源极和漏极区域。

公开(公告)号：WO2007103854A3

公开(公告)日：2008-04-10

申请号：PCT/US2007063275

申请日：2007-03-05

Applicant: IBM ,  CHIDAMBARRAO DURESETI

Inventor： CHIDAMBARRAO DURESETI

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7842

Abstract: An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate (600), comprising first areas having a first crystalline orientation and second areas having a second crystalline orientation. The first crystalline orientation of the first areas is not parallel or perpendicular to the second crystalline orientation of the second areas. The integrated circuit further comprises first type devices (620) on the first areas and second type devices (630) on the second areas, wherein the first type devices (620) are parallel or perpendicular to the second type devices (630), and the first type devices (620) comprise a first current flow (621) and a second current flow (622) orthogonal to each other, wherein the carrier mobilities of the first (621) and second (622) current flows are equal to each other. Specifically, the first type devices comprise p-type field effect transistors (PFETs) and the second type devices comprise n-type field effect transistors (NFETs).

Abstract translation: 本发明的实施例的集成电路包括混合取向衬底（600），其包括具有第一结晶取向的第一区域和具有第二结晶取向的第二区域。 第一区域的第一晶体取向不平行或垂直于第二区域的第二晶体取向。 集成电路还包括第一区域上的第一类型设备（620）和第二区域上的第二类型设备（630），其中第一类型设备（620）平行或垂直于第二类型设备（630），并且 第一类型装置（620）包括彼此正交的第一电流（621）和第二电流（622），其中第一（621）和第二（622）电流的载流子迁移率彼此相等。 具体地，第一类型器件包括p型场效应晶体管（PFET），第二类型器件包括n型场效应晶体管（NFET）。