公开(公告)号：US11314668B2

公开(公告)日：2022-04-26

申请号：US15898909

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/06 ,  G06F13/42

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

公开(公告)号：US20210408704A1

公开(公告)日：2021-12-30

申请号：US17470552

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  James McCall ,  Qin Li

IPC: H01R12/71 ,  H01R12/55 ,  H05K1/18 ,  H01R13/24

Abstract: Systems, apparatuses and methods may provide for a memory module that includes a dynamic random access memory (DRAM), a first plurality of contact pads positioned along a first side of the DRAM, a first plurality of L-shaped contacts, wherein each of the first plurality of L-shaped contacts is soldered to one of the first plurality of contact pads, a second plurality of contact pads positioned along a second side of the DRAM, and a second plurality of L-shaped contacts, wherein each of the second plurality of L-shaped contacts is soldered to one of the second plurality of contact pads.

公开(公告)号：US20210406206A1

公开(公告)日：2021-12-30

申请号：US17470278

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： George Vergis ,  John R. Goles

IPC: G06F13/16

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to enumerate respective sideband addresses to ten or more memory devices, and provide bi-directional communication with an individual memory device of the ten or more memory devices with a particular sideband address enumerated to the individual memory device. Other embodiments are disclosed and claimed.

公开(公告)号：US10969974B2

公开(公告)日：2021-04-06

申请号：US16112461

申请日：2018-08-24

Applicant: Intel Corporation

Inventor： George Vergis ,  Douglas Heymann ,  Dat Le ,  John Goles

IPC: G11C7/04 ,  G06F3/06 ,  G06F13/16 ,  G11C11/4074 ,  G11C5/14

Abstract: A memory controller includes a sensor poller and a proportional integral controller (PIC) coupled to the sensor poller. The sensor poller is to obtain a temperature and a power of a memory module (MM) operated by the controller, and the PIC is to: dynamically set at least one bandwidth limit for the MM, based, at least in part, on a relationship between a temperature of the MM, a power of the MM and a bandwidth of the MM. The dynamically set bandwidth limit defines the power of the MM at which the MM operates for a predetermined temperature limit. A system includes a memory controller and a dual in-line memory module (DIMM) operated by it.

公开(公告)号：US10790603B2

公开(公告)日：2020-09-29

申请号：US16264944

申请日：2019-02-01

Applicant: Intel Corporation

Inventor： Phil Geng ,  Xiang Li ,  George Vergis ,  Mani Prakash

IPC: H01R12/70 ,  H01R12/73

Abstract: An embodiment of a connector housing for a circuit board may include a connector body to receive the circuit board, and a relaxation mechanism mechanically coupled to the connector body to relax stress on the connector housing and maintain the circuit board received in the connector body under a load which exceeds a load threshold. Other embodiments are disclosed and claimed.

公开(公告)号：US20200050571A1

公开(公告)日：2020-02-13

申请号：US16655511

申请日：2019-10-17

Applicant: Intel Corporation

Inventor： Rajesh Bhaskar ,  Enrico Carrieri ,  Kenneth Foust ,  Janusz Jurski ,  Myron Loewen ,  Matthew A. Schnoor ,  Amit Kumar Srivastava ,  George Vergis

IPC: G06F13/40 ,  H04L29/08 ,  H04L12/18 ,  H04L12/40 ,  G06F1/10

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.

公开(公告)号：US20190044262A1

公开(公告)日：2019-02-07

申请号：US16021269

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Phil Geng ,  Xiang Li ,  Mani Prakash ,  George Vergis

IPC: H01R12/70 ,  H05K1/14 ,  H01R12/73

Abstract: A memory module connector includes a memory module receiving slot configured to receive a memory module. The memory module connector further includes a restraining mechanism configured to release the memory module if a force applied by the memory module to the restraining mechanism is above a pre-determined force threshold.

公开(公告)号：US10109941B1

公开(公告)日：2018-10-23

申请号：US15640394

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Xiang Li ,  George Vergis

IPC: H01R12/70 ,  H01R12/73 ,  H01R13/66 ,  H01R43/26

Abstract: One embodiment relates to a memory module connector comprising a housing defining a stepped slot configured to accept a memory module. Another embodiment includes a memory module defining a stepped slot configured to accept a memory module, and a memory module comprising a printed circuit board and a plurality of components mounted on the printed circuit board, wherein the wherein the stepped slot in the memory module connector is configured so that at least one of the plurality of components mounted on the printed circuit board is positioned in the stepped slot. Other embodiments are described and claimed.

公开(公告)号：US10067820B2

公开(公告)日：2018-09-04

申请号：US15650479

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C5/04 ,  G11C29/04

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.