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    Memory and resource management in a virtual computing environment
    32.
    发明授权
    Memory and resource management in a virtual computing environment 有权

    公开(公告)号：US10216532B2

    公开(公告)日：2019-02-26

    申请号：US14778520

    申请日：2014-09-12

    Applicant: Intel Corporation

    Inventor： Yao Zu Dong ,  Kun Tian

    IPC: G06F9/46 ,  G06F9/455 ,  G06F3/06

    Abstract: Systems and techniques for memory and resource management in a virtual computing environment are disclosed herein. For example, in some embodiments, an apparatus for memory management in a virtual computing environment may include: a storage device; memory page comparison logic, coupled to the storage device, to determine that a first memory page of instructions, stored in the storage device, for a guest machine in the virtual computing environment is identical to a second memory page of instructions, stored in the storage device, for a host machine in the virtual computing environment, wherein the guest machine is hosted by the host machine; and merge logic, coupled to the memory page comparison logic, to, in response to a determination that the first memory page is identical to the second memory page, map the first memory page to the second memory page. Other embodiments may be disclosed and/or claimed.

    Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
    34.
    发明授权
    Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications 有权

    公开(公告)号：US12174739B2

    公开(公告)日：2024-12-24

    申请号：US18392310

    申请日：2023-12-21

    Applicant: Intel Corporation

    Inventor： Yao Zu Dong ,  Kun Tian ,  Fengguang Wu ,  Jingqi Liu

    IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0802

    Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.

    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO CONTROL ADDRESS SPACE ISOLATION IN A VIRTUAL MACHINE
    35.
    发明申请
    METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO CONTROL ADDRESS SPACE ISOLATION IN A VIRTUAL MACHINE 有权

    公开(公告)号：US20240385970A1

    公开(公告)日：2024-11-21

    申请号：US18625880

    申请日：2024-04-03

    Applicant: Intel Corporation

    Inventor： Jun Tian ,  Kun Tian ,  Yu Zhang

    IPC: G06F12/1009 ,  G06F9/455 ,  G06F9/48 ,  G06F12/109

    Abstract: Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value, and generate a second GPA range based on the expanded emulated memory width value. The example apparatus also includes an EPT generator to generate root paging structures of a first type of EPT with respective addresses within the first GPA range, and generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.

    Methods and apparatus to process commands from virtual machines
    36.
    发明授权
    Methods and apparatus to process commands from virtual machines 有权

    公开(公告)号：US11947991B2

    公开(公告)日：2024-04-02

    申请号：US17845752

    申请日：2022-06-21

    Applicant: Intel Corporation

    Inventor： Yao Zu Dong ,  Yuankai Guo ,  Haozhong Zhang ,  Kun Tian

    IPC: G06F9/455 ,  G06F13/16

    CPC classification number: G06F9/45558 ,  G06F13/1668 ,  G06F2009/45579 ,  G06F2009/45583

    Abstract: A disclosed example includes accessing, by a backend block service driver in an input/output virtual machine executing on one or more processors, a first command submitted to a buffer by a paravirtualized input/output frontend block driver executing in a guest virtual machine; generating, by the backend block service driver, a translated command based on the first command by translating a virtual parameter of the first command to a physical parameter associated with a physical resource; submitting, by the backend block service driver, the translated command to an input/output queue to be processed by the physical resource based on the physical parameter; and submitting, by the backend block service driver, a completion status entry to the buffer, the completion status entry indicative of completion of a direct memory access operation that copies data between the physical resource and a guest memory buffer corresponding to the guest virtual machine.

    Scalable interrupt virtualization for input/output devices
    38.
    发明授权
    Scalable interrupt virtualization for input/output devices 有权

    公开(公告)号：US11734209B2

    公开(公告)日：2023-08-22

    申请号：US17550977

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  Utkarsh Y. Kakaiya ,  Kun Tian

    IPC: G06F13/28 ,  G06F13/24 ,  G06F9/455 ,  G06F9/48

    CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579

    Abstract: Implementations of the disclosure provide processing device comprising: an interrupt managing circuit to receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device. The interrupt message comprises an address space identifier (ASID), an interrupt handle and a flag to distinguish the interrupt message from a direct memory access (DMA) message. Responsive to receiving the interrupt message, a data structure associated with the interrupt managing circuit is identified. An interrupt entry from the data structure is selected based on the interrupt handle. It is determined that the ASID associated with the interrupt message matches an ASID in the interrupt entry. Thereupon, an interrupt in the interrupt entry is forwarded to the application container.

    Techniques for virtual machine transfer and resource management
    40.
    发明授权
    Techniques for virtual machine transfer and resource management 有权

    公开(公告)号：US11556363B2

    公开(公告)日：2023-01-17

    申请号：US16479395

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Sanjay Kumar ,  Philip R. Lantz ,  Kun Tian ,  Utkarsh Y. Kakaiya ,  Rajesh M. Sankaran

    IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

    Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

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