Patent search ap:("INTEL CORPORATION") AND inv:"Mike Macpherson" Page 4

31.

发明授权
Instruction based control of memory attributes 有权

公开(公告)号：US11899614B2

公开(公告)日：2024-02-13

申请号：US17849201

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Joydeep Ray , Altug Koker , Varghese George , Mike Macpherson , Aravindh Anantaraman , Abhishek R. Appu , Elmoustapha Ould-Ahmed-Vall , Nicolas Galoppo von Borries , Ben J. Ashbaugh

IPC: G06F15/78 , G06F9/30 , G06F9/38 , G06F17/18 , G06F12/0802 , G06F7/544 , G06F7/575 , G06F12/02 , G06F12/0866 , G06F12/0875 , G06F12/0895 , G06F12/128 , G06F12/06 , G06F12/1009 , G06T1/20 , G06T1/60 , H03M7/46 , G06F12/0811 , G06F15/80 , G06F17/16 , G06F7/58 , G06F12/0871 , G06F12/0862 , G06F12/0897 , G06F9/50 , G06F12/0804 , G06F12/0882 , G06F12/0891 , G06F12/0893 , G06F12/0888 , G06T15/06 , G06N3/08

CPC classification number: G06F15/7839 , G06F7/5443 , G06F7/575 , G06F7/588 , G06F9/3001 , G06F9/3004 , G06F9/30014 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30065 , G06F9/30079 , G06F9/3887 , G06F9/5011 , G06F9/5077 , G06F12/0215 , G06F12/0238 , G06F12/0246 , G06F12/0607 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0862 , G06F12/0866 , G06F12/0871 , G06F12/0875 , G06F12/0882 , G06F12/0888 , G06F12/0891 , G06F12/0893 , G06F12/0895 , G06F12/0897 , G06F12/1009 , G06F12/128 , G06F15/8046 , G06F17/16 , G06F17/18 , G06T1/20 , G06T1/60 , H03M7/46 , G06F9/3802 , G06F9/3818 , G06F9/3867 , G06F2212/1008 , G06F2212/1021 , G06F2212/1044 , G06F2212/302 , G06F2212/401 , G06F2212/455 , G06F2212/60 , G06N3/08 , G06T15/06

Abstract: Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

32.

发明申请
TOOL FOR FACILITATING EFFICIENCY IN MACHINE LEARNING 有权

公开(公告)号：US20230017304A1

公开(公告)日：2023-01-19

申请号：US17874876

申请日：2022-07-27

Applicant: Intel Corporation

Inventor： Rajkishore Barik , Brian T. Lewis , Murali Sundaresan , Jeffrey Jackson , Feng Chen , Xiaoming Chen , Mike Macpherson

IPC: G06N3/063 , G06N3/04 , G06N3/08 , G06N5/00 , G06F9/46

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

33.

发明申请
DATA INITIALIZATION TECHNIQUES 有权

公开(公告)号：US20220129271A1

公开(公告)日：2022-04-28

申请号：US17430963

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu , Aravindh Anantaraman , Elmoustapha Ould-Ahmed-Vall , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Altug Koker , Mike Macpherson , Subramaniam Maiyuran , Joydeep Ray , Vasanth Ranganathan

IPC: G06F9/30 , G06F12/0871 , G06F12/0811 , G06F7/58 , G06T15/06

Abstract: Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.

34.

发明申请
MULTI-TILE MEMORY MANAGEMENT 有权

公开(公告)号：US20220121421A1

公开(公告)日：2022-04-21

申请号：US17431034

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu , Altug Koker , Aravindh Anantaraman , Elmoustapha Ould-Ahmed-Vall , Valentin Andrei , Nicolas Galoppo Von Borries , Varghese George , Mike Macpherson , Subramaniam Maiyuran , Joydeep Ray , Lakshminarayana Striramassarma , Scott Janus , Brent Insko , Vasanth Ranganathan , Kamal Sinha , Arthur Hunter , Prasoonkumar Surti , David Puffer , James Valerio , Ankur N. Shah

IPC: G06F7/575 , G06F7/544 , G06F9/30 , G06F9/38 , G06F12/128 , G06F12/0875 , G06F12/0866 , G06F12/0895 , G06F12/02

Abstract: Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

35.

发明申请
LOCAL MEMORY SHARING BETWEEN KERNELS 有权

公开(公告)号：US20220058053A1

公开(公告)日：2022-02-24

申请号：US17472975

申请日：2021-09-13

Applicant: Intel Corporation

Inventor： Valentin Andrei , Aravindh Anantaraman , Abhishek R. Appu , Nicolas C. Galoppo von Borries , Altug Koker , SungYe Kim , Elmoustapha Ould-Ahmed-Vall , Mike Macpherson , Subramaniam Maiyuran , Vasanth Ranganathan , Joydeep Ray , Varghese George

IPC: G06F9/48 , G06F13/16 , G06F13/42 , G06N3/08

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a set of processing elements to execute one or more thread groups of a second kernel to be executed by the general-purpose graphics processor, an on-chip memory coupled to the set of processing elements, and a scheduler coupled with the set of processing elements, the scheduler to schedule the thread groups of the kernel to the set of processing elements, wherein the scheduler is to schedule a thread group of the second kernel to execute subsequent to a thread group of a first kernel, the thread group of the second kernel configured to access a region of the on-chip memory that contains data written by the thread group of the first kernel in response to a determination that the second kernel is dependent upon the first kernel.

36.

发明申请
SPARSE OPTIMIZATOINS FOR A MATRIX ACCELERATOR ARCHITECTURE 有权

公开(公告)号：US20210035258A1

公开(公告)日：2021-02-04

申请号：US17064427

申请日：2020-10-06

Applicant: Intel Corporation

Inventor： Joydeep Ray , Scott Janus , Varghese George , Subramaniam Maiyuran , Altug Koker , Abhishek Appu , Prasoonkumar Surti , Vasanth Ranganathan , Andrei Valentin , Ashutosh Garg , Yoav Harel , Arthur Hunter, JR. , SungYe Kim , Mike Macpherson , Elmoustapha Ould-Ahmed-Vall , William Sadler , Lakshminarayanan Striramassarma , Vikranth Vemulapalli

IPC: G06T1/20 , G06F9/50 , G06F15/80 , G06F12/0806 , G06N3/04 , G06N3/08 , G06F17/16

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

37.

发明申请
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT 审中-公开

公开(公告)号：US20200294179A1

公开(公告)日：2020-09-17

申请号：US16355274

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Joydeep Ray , Aravindh Anantaraman , Valentin Andrei , Abhishek R. Appu , Nicolas Galoppo von Borries , Varghese George , Altug Koker , Elmoustapha Ould-Ahmed-Vall , Mike Macpherson , Subramaniam Maiyuran

IPC: G06T1/20 , G06T1/60 , G06F9/38 , G06T15/00

Abstract: Embodiments are generally directed to memory prefetching in multiple GPU environment. An embodiment of an apparatus includes multiple processors including a host processor and multiple graphics processing units (GPUs) to process data, each of the GPUs including a prefetcher and a cache; and a memory for storage of data, the memory including a plurality of memory elements, wherein the prefetcher of each of the GPUs is to prefetch data from the memory to the cache of the GPU; and wherein the prefetcher of a GPU is prohibited from prefetching from a page that is not owned by the GPU or by the host processor.

38.

发明授权
Sparse optimizations for a matrix accelerator architecture 有权

公开(公告)号：US12293431B2

公开(公告)日：2025-05-06

申请号：US18310688

申请日：2023-05-02

Applicant: Intel Corporation

Inventor： Joydeep Ray , Scott Janus , Varghese George , Subramaniam Maiyuran , Altug Koker , Abhishek Appu , Prasoonkumar Surti , Vasanth Ranganathan , Valentin Andrei , Ashutosh Garg , Yoav Harel , Arthur Hunter, Jr. , SungYe Kim , Mike Macpherson , Elmoustapha Ould-Ahmed-Vall , William Sadler , Lakshminarayanan Striramassarma , Vikranth Vemulapalli

IPC: G06T1/20 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/0806 , G06F15/80 , G06F17/16 , G06N3/048 , G06N3/08 , G06N3/084

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

39.

发明申请
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY 有权

公开(公告)号：US20250104180A1

公开(公告)日：2025-03-27

申请号：US18967172

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Abhishek Appu , Subramaniam Maiyuran , Mike Macpherson , Fangwen Fu , Jiasheng Chen , Varghese George , Vasanth Ranganathan , Ashutosh Garg , Joydeep Ray

IPC: G06T1/20 , G06F7/544 , G06F9/30 , G06F9/38 , G06F9/50 , G06F12/0806 , G06F15/80 , G06F17/16 , G06N3/048 , G06N3/08 , G06N3/084

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.